radeonsi: add support for PKT3 cmds to new state handling
authorChristian König <deathsimple@vodafone.de>
Thu, 2 Aug 2012 12:30:06 +0000 (14:30 +0200)
committerChristian König <deathsimple@vodafone.de>
Sat, 11 Aug 2012 07:58:25 +0000 (09:58 +0200)
Signed-off-by: Christian König <deathsimple@vodafone.de>
src/gallium/drivers/radeonsi/radeonsi_pm4.c
src/gallium/drivers/radeonsi/radeonsi_pm4.h

index 12facafbfa891feb0c0fcb3b1f7aa2a68a4c4aee..da680dc1ee13d6105cf802c444393caab8b7803f 100644 (file)
 
 #define NUMBER_OF_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
 
+void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
+{
+       state->last_opcode = opcode;
+       state->last_pm4 = state->ndw++;
+}
+
+void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
+{
+       state->pm4[state->ndw++] = dw;
+}
+
+void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
+{
+       unsigned count;
+       count = state->ndw - state->last_pm4 - 2;
+       state->pm4[state->last_pm4] = PKT3(state->last_opcode,
+                                          count, predicate);
+
+       assert(state->ndw <= SI_PM4_MAX_DW);
+}
+
 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
 {
-       unsigned opcode, count;
+       unsigned opcode;
 
        if (reg >= SI_CONFIG_REG_OFFSET && reg <= SI_CONFIG_REG_END) {
                opcode = PKT3_SET_CONFIG_REG;
@@ -55,17 +76,13 @@ void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
        reg >>= 2;
 
        if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
-               state->last_opcode = opcode;
-               state->last_pm4 = state->ndw++;
-               state->pm4[state->ndw++] = reg;
+               si_pm4_cmd_begin(state, opcode);
+               si_pm4_cmd_add(state, reg);
        }
 
        state->last_reg = reg;
-       count = state->ndw - state->last_pm4 - 1;
-       state->pm4[state->last_pm4] = PKT3(opcode, count, 0);
-       state->pm4[state->ndw++] = val;
-
-       assert(state->ndw <= SI_PM4_MAX_DW);
+       si_pm4_cmd_add(state, val);
+       si_pm4_cmd_end(state, false);
 }
 
 void si_pm4_add_bo(struct si_pm4_state *state,
index 18e51831e8fd427b1a2c27906ae36c35424a3dfb..bbddfd01a2d5f3e3304ae0944484eabb45147453 100644 (file)
@@ -55,6 +55,10 @@ struct si_pm4_state
        enum radeon_bo_usage    bo_usage[SI_PM4_MAX_BO];
 };
 
+void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode);
+void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw);
+void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate);
+
 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
 void si_pm4_add_bo(struct si_pm4_state *state,
                   struct si_resource *bo,