set sv_mode to 0b01 in element-strided

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index cf26f43f3e274625eca9cdfc2a1ecc57c9d0be43..596514cdbb6ba99f29defc1b039c2bb7f07e67be 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1030,6 +1030,7 @@ class SVP64Asm:
         # identify if the op is a LD/ST. 
         # see https://libre-soc.org/openpower/sv/ldst/
         is_ldst = rm['mode'] in [ 'LDST_IDX', 'LDST_IMM']
+        is_ldst_idx = rm['mode'] ==  'LDST_IDX'
         is_ld = v30b_op.startswith("l") and is_ldst
         is_st = v30b_op.startswith("s") and is_ldst
 
@@ -1101,6 +1102,9 @@ class SVP64Asm:
             # element-strided LD/ST
             elif encmode == 'els':
                 ldst_elstride = 1
+                # in indexed mode, set sv_mode=0b01
+                if is_ldst_idx:
+                    sv_mode = 0b01
             # saturation
             elif encmode == 'sats':
                 assert sv_mode is None