is prohibited in the Simple-V Scalable Vector ISA,
This does
mean that `RESERVED` space is crucial to have, in order
-to safely provide future expanded register file bitwidths and sizes[^msr]
+to safely provide the option of
+future expanded register file bitwidths and sizes[^msr],
+under explicitly-distinguishable encoding,
**at the discretion of and with the full authority of the OPF ISA WG**,
not the implementor ("Silicon Partner").
[REMAP](https://libre-soc.org/openpower/sv/remap)
is extremely advanced but brings features already present in other
-DSPs and Supercomputing ISAs.
+DSPs and Supercomputing ISAs. Normally (without these features)
+algorithms are are costly or
+convoluted to implement. They are typically implemented
+as hard-coded fully loop-unrolled assembler which is often
+auto-generated by specialist dedicated tools, or written
+entirely by hand.
+
+All REMAP Schedules *including Indexed*
+are 100% Deterministic from their point of declaration,
+making it possible to forward-plan
+Issue, Memory access and Register Hazard Management
+in Multi-Issue Micro-architectures.
* **DCT/FFT** REMAP brings more capability than TI's MSP-Series DSPs and
Qualcom Hexagon DSPs, and is not restricted to Integer or FP.
suited to Convolutions, Matrix Transpose and rotate, *all* of which is
in-place.
* **General-purpose Indexed** REMAP, this option is provided to implement
- an equivalent of VSX `vperm`
+ an equivalent of VSX `vperm`, as a general-purpose catch-all means of
+ covering algorithms outside of the other REMAP Engines.
* **Parallel Reduction** REMAP, performs an automatic map-reduce using
*any suitable scalar operation*.