Bugfix in Xilinx LUT mapping

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index ee67beba7ace028f7f2686ef55831673799fc1f9..fbcc96014df4f8099beea3bf5a9e568d561ce2c6 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -204,7 +204,7 @@ struct SynthXilinxPass : public Pass {
 
                if (check_label(active, run_from, run_to, "map_luts"))
                {
-                       Pass::call(design, "abc -lut 5:8" + string(retime ? " -dff" : ""));
+                       Pass::call(design, "abc -lut 6:8" + string(retime ? " -dff" : ""));
                        Pass::call(design, "clean");
                }