warning (0, "multiply option implies r%d is fixed", regno);
fixed_regs [regno] = call_used_regs[regno] = 1;
}
- if (TARGET_Q_CLASS)
- {
- if (optimize_size)
- {
- reg_alloc_order[0] = 0;
- reg_alloc_order[1] = 1;
- reg_alloc_order[2] = 2;
- reg_alloc_order[3] = 3;
- reg_alloc_order[4] = 12;
- reg_alloc_order[5] = 13;
- reg_alloc_order[6] = 14;
- reg_alloc_order[7] = 15;
- reg_alloc_order[8] = 4;
- reg_alloc_order[9] = 5;
- reg_alloc_order[10] = 6;
- reg_alloc_order[11] = 7;
- reg_alloc_order[12] = 8;
- reg_alloc_order[13] = 9;
- reg_alloc_order[14] = 10;
- reg_alloc_order[15] = 11;
- }
- else
- {
- reg_alloc_order[2] = 12;
- reg_alloc_order[3] = 13;
- reg_alloc_order[4] = 14;
- reg_alloc_order[5] = 15;
- reg_alloc_order[6] = 1;
- reg_alloc_order[7] = 0;
- reg_alloc_order[8] = 4;
- reg_alloc_order[9] = 5;
- reg_alloc_order[10] = 6;
- reg_alloc_order[11] = 7;
- reg_alloc_order[12] = 8;
- reg_alloc_order[13] = 9;
- reg_alloc_order[14] = 10;
- reg_alloc_order[15] = 11;
- }
- }
- if (TARGET_SIMD_SET)
- {
- int i;
- for (i = ARC_FIRST_SIMD_VR_REG; i <= ARC_LAST_SIMD_VR_REG; i++)
- reg_alloc_order [i] = i;
- for (i = ARC_FIRST_SIMD_DMA_CONFIG_REG;
- i <= ARC_LAST_SIMD_DMA_CONFIG_REG; i++)
- reg_alloc_order [i] = i;
- }
/* Reduced configuration: don't use r4-r9, r16-r25. */
if (TARGET_RF16)
return false;
}
+/* This order of allocation is used when we compile for size. It
+ allocates first the registers which are most probably to end up in
+ a short instruction. */
+static const int size_alloc_order[] =
+{
+ 0, 1, 2, 3, 12, 13, 14, 15,
+ 4, 5, 6, 7, 8, 9, 10, 11
+};
+
+/* Adjust register allocation order when compiling for size. */
+void
+arc_adjust_reg_alloc_order (void)
+{
+ const int arc_default_alloc_order[] = REG_ALLOC_ORDER;
+ memcpy (reg_alloc_order, arc_default_alloc_order, sizeof (reg_alloc_order));
+ if (optimize_size)
+ memcpy (reg_alloc_order, size_alloc_order, sizeof (size_alloc_order));
+}
+
#undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
#define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
By default, the extension registers are not available. */
/* Present implementations only have VR0-VR23 only. */
-/* ??? FIXME: r27 and r31 should not be fixed registers. */
#define FIXED_REGISTERS \
{ 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
/* If defined, an initializer for a vector of integers, containing the
numbers of hard registers in the order in which GCC should
prefer to use them (from most preferred to least). */
-#define REG_ALLOC_ORDER \
-{ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \
- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
+#define REG_ALLOC_ORDER \
+{ \
+ /* General registers. */ \
+ 2, 3, 12, 13, 14, 15, 1, 0, 4, 5, 6, 7, 8, 9, 10, 11, \
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 30, \
+ /* Extension core registers. */ \
32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
- 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
- 27, 28, 29, 30, 31, 63}
+ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
+ /* VR regs. */ \
+ 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+ 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
+ 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+ 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, \
+ 124, 125, 126, 127, \
+ /* DMA registers. */ \
+ 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, \
+ 142, 143, \
+ /* Register not used for general use. */ \
+ 62, FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
+ SP_REG, ILINK1_REG, RETURN_ADDR_REGNUM, LP_COUNT, CC_REG, PCL_REG \
+}
+
+/* Use different register alloc ordering for Thumb. */
+#define ADJUST_REG_ALLOC_ORDER arc_adjust_reg_alloc_order ()
+
+/* Tell IRA to use the order we define rather than messing it up with its
+ own cost calculations. */
+#define HONOR_REG_ALLOC_ORDER 1
/* Internal macros to classify a register number as to whether it's a
general purpose register for compact insns (r0-r3,r12-r15), or
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