Implement a handful more instructions and differentiate macroops based on the operand...

--HG--
extra : convert_revision : f9c8e694a8c0eb33b988657dca03ab495b65bee8

diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 72fbf289690e11a1c91ce88447ef9c4dd68a8478..b72b2b16a9df7ae28905120990c8f4ad02c3f8d5 100644 (file)
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -163,11 +163,11 @@
             0x7: dec_eDI();
         }
         0x0A: decode OPCODE_OP_BOTTOM3 {
-            0x0: push_rAX();
+            0x0: Inst::PUSH(rAx);
             0x1: push_rCX();
             0x2: push_rDX();
             0x3: push_rBX();
-            0x4: push_rSP();
+            0x4: Inst::PUSH(rSP);
             0x5: push_rBP();
             0x6: push_rSI();
             0x7: push_rDI();
@@ -230,7 +230,17 @@
             0x0: group1_Eb_Ib();
             0x1: group1_Ev_Iz();
             0x2: group1_Eb_Ib();
-            0x3: group1_Ev_Ib();
+            //0x3: group1_Ev_Ib();
+            0x3: decode MODRM_REG {
+                0x0: add_Eb_Ib();
+                0x1: or_Eb_Ib();
+                0x2: adc_Eb_Ib();
+                0x3: sbb_Eb_Ib();
+                0x4: Inst::AND(Eb,Ib);
+                0x5: sub_Eb_Ib();
+                0x6: xor_Eb_Ib();
+                0x7: cmp_Eb_Ib();
+            }
             0x4: test_Eb_Gb();
             0x5: test_Ev_Gv();
             0x6: xchg_Eb_Gb();
@@ -313,8 +323,14 @@
             0x3: ret_near();
             0x4: les_Gz_Mp();
             0x5: lds_Gz_Mp();
-            0x6: group12_Eb_Ib();
-            0x7: group12_Ev_Iz();
+            //0x6: group12_Eb_Ib();
+            0x6: decode MODRM_REG {
+                0x0: Inst::MOV(Eb,Ib);
+            }
+            //0x7: group12_Ev_Iz();
+            0x7: decode MODRM_REG {
+                0x0: Inst::MOV(Ev,Iz);
+            }
         }
         0x19: decode OPCODE_OP_BOTTOM3 {
             0x0: enter_Iw_Ib();

diff --git a/src/arch/x86/isa/formats/multi.isa b/src/arch/x86/isa/formats/multi.isa
index f951dc28a338d7bb6cc28456dd28ece746f3b276..37b28fe647d9d2252e9aad1cab1e019f964af624 100644 (file)
--- a/src/arch/x86/isa/formats/multi.isa
+++ b/src/arch/x86/isa/formats/multi.isa
@@ -70,8 +70,8 @@ def format Inst(*opTypeSet) {{
 def format MultiInst(switchVal, *opTypeSets) {{
     switcher = {}
     for (count, opTypeSet) in zip(xrange(len(opTypeSets)), opTypeSets):
-        switcher[count] = (opTypeSet, EmulEnv())
-    blocks = doSplitDecode(Name, specializeInst, switchVal, switcher)
+        switcher[count] = (Name, opTypeSet, EmulEnv())
+    blocks = doSplitDecode(specializeInst, switchVal, switcher)
     (header_output, decoder_output,
      decode_block, exec_output) = blocks.makeList()
 }};

diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py
index acfe2f516d02b6d768b92f5fb17410f56503e87b..9d23b24e8d8991871bb3f8bb86d503426ab60538 100644 (file)
--- a/src/arch/x86/isa/insts/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/data_transfer/move.py
@@ -54,9 +54,26 @@
 # Authors: Gabe Black
 
 microcode = '''
-def macroop MOV{
+def macroop MOV_R_R {
     mov "env.reg", "env.reg", "env.regm"
 };
+
+def macroop MOV_M_R {
+    #Do a store to put the register operand into memory
+};
+
+def macroop MOV_R_M {
+    #Do a load to fill the register operand from memory
+};
+
+def macroop MOV_R_I {
+    limm "env.reg", "env.immediate"
+};
+
+def macroop MOV_M_I {
+    limm "env.reg", "env.immediate"
+    #Do a store to put the register operand into memory
+};
 '''
 #let {{
 #    class MOV(Inst):

diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
index fff0f749f6911c59460fb33784b8e733e56d0217..b7ec0ec669626275f631763dcca691def7078ecc 100644 (file)
--- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
@@ -54,11 +54,17 @@
 # Authors: Gabe Black
 
 microcode = '''
-def macroop POP {
+def macroop POP_R {
     .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
     # There needs to be a load here to actually "pop" the data
     addi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
 };
+
+def macroop PUSH_R {
+    .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
+    subi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
+    # There needs to be a store here to actually "push" the data
+};
 '''
 #let {{
 #    class POP(Inst):

diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py
index fee631da77924cd8c0e3aa5924b5a41465698a50..ec0ed97b29dc3d650b344885967a77ae9dbcdde2 100644 (file)
--- a/src/arch/x86/isa/insts/logical.py
+++ b/src/arch/x86/isa/insts/logical.py
@@ -54,10 +54,43 @@
 # Authors: Gabe Black
 
 microcode = '''
-def macroop XOR
+def macroop XOR_R_R
 {
     xor "env.reg", "env.reg", "env.regm"
 };
+
+def macroop XOR_R_I
+{
+    limm "NUM_INTREGS", "env.immediate"
+    xor "env.reg", "env.reg", "NUM_INTREGS"
+};
+
+def macroop XOR_M_R
+{
+    #Do a load to get one of the sources
+    xor "NUM_INTREGS", "NUM_INTREGS", "env.reg"
+    #Do a store to write the destination
+};
+
+def macroop XOR_R_M
+{
+    #Do a load to get one of the sources
+    xor "env.reg", "env.reg", "NUM_INTREGS"
+};
+
+def macroop AND_R_I
+{
+    limm "NUM_INTREGS", "env.immediate"
+    and "env.reg", "env.reg", "NUM_INTREGS"
+};
+
+def macroop AND_M_I
+{
+    #Do a load to get one of the sources
+    limm "NUM_INTREGS", "env.immediate"
+    and "NUM_INTREGS", "NUM_INTREGS", "NUM_INTREGS+1"
+    #Do a store to write the destination
+};
 '''
 #let {{
 #microcodeString = '''

diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa
index 96add3ab5a8d9b74cb995f7903b11587a9988524..faf86335187064d57bb8d7a0b062969dfd1e5dd8 100644 (file)
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -66,16 +66,16 @@ let {{
     # vals is a dict which matches case values with what should be decoded to.
     # builder is called on the exploded contents of "vals" values to generate
     # whatever code should be used.
-    def doSplitDecode(Name, builder, switchVal, vals, default = None):
+    def doSplitDecode(builder, switchVal, vals, default = None):
         blocks = OutputBlocks()
         blocks.decode_block = 'switch(%s) {\n' % switchVal
         for (val, todo) in vals.items():
-            new_blocks = builder(Name, *todo)
+            new_blocks = builder(*todo)
             new_blocks.decode_block = \
                 '\tcase %s: %s\n' % (val, new_blocks.decode_block)
             blocks.append(new_blocks)
         if default:
-            new_blocks = builder(Name, *default)
+            new_blocks = builder(*default)
             new_blocks.decode_block = \
                 '\tdefault: %s\n' % new_blocks.decode_block
             blocks.append(new_blocks)
@@ -120,11 +120,13 @@ let {{
                         print "word"
                     else:
                         print "Didn't recognize fixed register size %s!" % opType.rsize
+                Name += "_R"
             elif opType.tag == None or opType.size == None:
                 raise Exception, "Problem parsing operand tag: %s" % opType.tag
             elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"):
                 # Use the "reg" field of the ModRM byte to select the register
                 env.addReg(ModRMRegIndex)
+                Name += "_R"
             elif opType.tag in ("E", "Q", "W"):
                 # This might refer to memory or to a register. We need to
                 # divide it up farther.
@@ -132,27 +134,33 @@ let {{
                 regTypes.pop(0)
                 regEnv = copy.copy(env)
                 regEnv.addReg(ModRMRMIndex)
+                regName = Name + "_R"
                 # This needs to refer to memory, but we'll fill in the details
                 # later. It needs to take into account unaligned memory
                 # addresses.
                 memTypes = copy.copy(opTypes)
                 memTypes.pop(0)
                 memEnv = copy.copy(env)
+                memName = Name + "_M"
                 print "%0"
-                return doSplitDecode(Name, specializeInst, "MODRM_MOD",
-                    {"3" : (regTypes, regEnv)}, (memTypes, memEnv))
+                return doSplitDecode(specializeInst, "MODRM_MOD",
+                    {"3" : (regName, regTypes, regEnv)},
+                    (memName, memTypes, memEnv))
             elif opType.tag in ("I", "J"):
                 # Immediates
                 print "IMMEDIATE"
+                Name += "_I"
             elif opType.tag == "M":
                 # This needs to refer to memory, but we'll fill in the details
                 # later. It needs to take into account unaligned memory
                 # addresses.
                 print "%0"
+                Name += "_M"
             elif opType.tag in ("PR", "R", "VR"):
                 # There should probably be a check here to verify that mod
                 # is equal to 11b
                 env.addReg(ModRMRMIndex)
+                Name += "_R"
             else:
                 raise Exception, "Unrecognized tag %s." % opType.tag
             opTypes.pop(0)