[PR target/97726] arm: [testsuite] fix some simd tests on armbe

2020-11-10  Andrea Corallo  <andrea.corallo@arm.com>

	PR target/97726
	* gcc.target/arm/simd/bf16_vldn_1.c: Relax regexps not to fail on
	big endian.
	* gcc.target/arm/simd/vldn_lane_bf16_1.c: Likewise
	* gcc.target/arm/simd/vmmla_1.c: Add -mfloat-abi=hard flag.

diff --git a/gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c b/gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c
index 222e7af945383bd93b6b280b516a56e684f1d651..663e76984c3b1384e341ef747ba2013099290917 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c
@@ -10,8 +10,8 @@
 /*
 **test_vld2_bf16:
 **     ...
-**     vld2.16 {d0-d1}, \[r0\]
-**     bx      lr
+**     vld[0-9]+.16    {d[0-9]+-d[0-9]+}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x4x2_t
 test_vld2_bf16 (bfloat16_t * ptr)
@@ -22,8 +22,8 @@ test_vld2_bf16 (bfloat16_t * ptr)
 /*
 **test_vld2q_bf16:
 **     ...
-**     vld2.16 {d0-d3}, \[r0\]
-**     bx      lr
+**     vld[0-9]+.16    {d[0-9]+-d[0-9]+}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x8x2_t
 test_vld2q_bf16 (bfloat16_t * ptr)
@@ -34,8 +34,8 @@ test_vld2q_bf16 (bfloat16_t * ptr)
 /*
 **test_vld2_dup_bf16:
 **     ...
-**     vld2.16 {d0\[\], d1\[\]}, \[r0\]
-**     bx      lr
+**     vld[0-9]+.16    {d[0-9]+\[\], d[0-9]+\[\]}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x4x2_t
 test_vld2_dup_bf16 (bfloat16_t * ptr)
@@ -46,8 +46,8 @@ test_vld2_dup_bf16 (bfloat16_t * ptr)
 /*
 **test_vld2q_dup_bf16:
 **     ...
-**     vld2.16 {d0, d1, d2, d3}, \[r0\]
-**     bx      lr
+**     vld[0-9]+.16    {d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x8x2_t
 test_vld2q_dup_bf16 (bfloat16_t * ptr)
@@ -58,8 +58,8 @@ test_vld2q_dup_bf16 (bfloat16_t * ptr)
 /*
 **test_vld3_bf16:
 **     ...
-**     vld3.16 {d0-d2}, \[r0\]
-**     bx      lr
+**     vld[0-9]+.16    {d[0-9]+-d[0-9]+}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x4x3_t
 test_vld3_bf16 (bfloat16_t * ptr)
@@ -70,8 +70,8 @@ test_vld3_bf16 (bfloat16_t * ptr)
 /*
 **test_vld3q_bf16:
 **     ...
-**     vld3.16 {d1, d3, d5}, \[r0\]
-**     bx      lr
+**     vld[0-9]+.16    {d[0-9]+, d[0-9]+, d[0-9]+}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x8x3_t
 test_vld3q_bf16 (bfloat16_t * ptr)
@@ -82,8 +82,8 @@ test_vld3q_bf16 (bfloat16_t * ptr)
 /*
 **test_vld3_dup_bf16:
 **     ...
-**     vld3.16 {d0\[\], d1\[\], d2\[\]}, \[r0\]
-**     bx      lr
+**     vld[0-9]+.16    {d[0-9]+\[\], d[0-9]+\[\], d[0-9]+\[\]}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x4x3_t
 test_vld3_dup_bf16 (bfloat16_t * ptr)
@@ -94,8 +94,8 @@ test_vld3_dup_bf16 (bfloat16_t * ptr)
 /*
 **test_vld3q_dup_bf16:
 **     ...
-**     vld3.16 {d0\[\], d1\[\], d2\[\]}, \[r0\]
-**     bx      lr
+**     vld[0-9]+.16    {d[0-9]+\[\], d[0-9]+\[\], d[0-9]+\[\]}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x8x3_t
 test_vld3q_dup_bf16 (bfloat16_t * ptr)
@@ -106,8 +106,8 @@ test_vld3q_dup_bf16 (bfloat16_t * ptr)
 /*
 **test_vld4_bf16:
 **     ...
-**     vld4.16 {d0-d3}, \[r0\]
-**     bx      lr
+**     vld4.16 {d[0-9]+-d[0-9]+}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x4x4_t
 test_vld4_bf16 (bfloat16_t * ptr)
@@ -118,8 +118,8 @@ test_vld4_bf16 (bfloat16_t * ptr)
 /*
 **test_vld4q_bf16:
 **     ...
-**     vld4.16 {d1, d3, d5, d7}, \[r0\]
-**     bx      lr
+**     vld4.16 {d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x8x4_t
 test_vld4q_bf16 (bfloat16_t * ptr)
@@ -130,8 +130,8 @@ test_vld4q_bf16 (bfloat16_t * ptr)
 /*
 **test_vld4_dup_bf16:
 **     ...
-**     vld4.16 {d0\[\], d1\[\], d2\[\], d3\[\]}, \[r0\]
-**     bx      lr
+**     vld4.16 {d[0-9]+\[\], d[0-9]+\[\], d[0-9]+\[\], d[0-9]+\[\]}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x4x4_t
 test_vld4_dup_bf16 (bfloat16_t * ptr)
@@ -142,8 +142,8 @@ test_vld4_dup_bf16 (bfloat16_t * ptr)
 /*
 **test_vld4q_dup_bf16:
 **     ...
-**     vld4.16 {d0\[\], d1\[\], d2\[\], d3\[\]}, \[r0\]
-**     bx      lr
+**     vld4.16 {d[0-9]+\[\], d[0-9]+\[\], d[0-9]+\[\], d[0-9]+\[\]}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x8x4_t
 test_vld4q_dup_bf16 (bfloat16_t * ptr)

diff --git a/gcc/testsuite/gcc.target/arm/simd/vldn_lane_bf16_1.c b/gcc/testsuite/gcc.target/arm/simd/vldn_lane_bf16_1.c
index 58153eddf6239c76be9a6da621a5836836085efa..b235b1f33b9cdf2d68389f72ca31241869b371ff 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/simd/vldn_lane_bf16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vldn_lane_bf16_1.c
@@ -8,8 +8,9 @@
 
 /*
 **test_vld2_lane_bf16:
-**     vld2.16 {d0\[2\], d1\[2\]}, \[r0\]
-**     bx      lr
+**     ...
+**     vld2.16 {d[0-9]+\[2\], d[0-9]+\[2\]}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x4x2_t
 test_vld2_lane_bf16 (const bfloat16_t *a, bfloat16x4x2_t b)
@@ -19,8 +20,9 @@ test_vld2_lane_bf16 (const bfloat16_t *a, bfloat16x4x2_t b)
 
 /*
 **test_vld2q_lane_bf16:
-**     vld2.16 {d0\[2\], d2\[2\]}, \[r0\]
-**     bx      lr
+**     ...
+**     vld2.16 {d[0-9]+\[2\], d[0-9]+\[2\]}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x8x2_t
 test_vld2q_lane_bf16 (const bfloat16_t *a, bfloat16x8x2_t b)
@@ -30,8 +32,9 @@ test_vld2q_lane_bf16 (const bfloat16_t *a, bfloat16x8x2_t b)
 
 /*
 **test_vld3_lane_bf16:
-**     vld3.16 {d0\[2\], d1\[2\], d2\[2\]}, \[r0\]
-**     bx      lr
+**     ...
+**     vld3.16 {d[0-9]+\[2\], d[0-9]+\[2\], d[0-9]+\[2\]}, \[r[0-9]+\]
+**     ...
 */
 bfloat16x4x3_t
 test_vld3_lane_bf16 (const bfloat16_t *a, bfloat16x4x3_t b)
@@ -41,8 +44,9 @@ test_vld3_lane_bf16 (const bfloat16_t *a, bfloat16x4x3_t b)
 
 /*
 **test_vld3q_lane_bf16:
-**     vld3.16 {d0\[2\], d2\[2\], d4\[2\]}, \[r0\]
-**     bx      lr
+**     ...
+**     vld3.16 {d[0-9]+\[2\], d[0-9]+\[2\], d[0-9]+\[2\]}, \[r0\]
+**     ...
 */
 bfloat16x8x3_t
 test_vld3q_lane_bf16 (const bfloat16_t *a, bfloat16x8x3_t b)
@@ -52,8 +56,9 @@ test_vld3q_lane_bf16 (const bfloat16_t *a, bfloat16x8x3_t b)
 
 /*
 **test_vld4_lane_bf16:
-**     vld4.16 {d0\[2\], d1\[2\], d2\[2\], d3\[2\]}, \[r0\]
-**     bx      lr
+**     ...
+**     vld4.16 {d[0-9]+\[2\], d[0-9]+\[2\], d[0-9]+\[2\], d[0-9]+\[2\]}, \[r0\]
+**     ...
 */
 bfloat16x4x4_t
 test_vld4_lane_bf16 (const bfloat16_t *a, bfloat16x4x4_t b)
@@ -63,8 +68,9 @@ test_vld4_lane_bf16 (const bfloat16_t *a, bfloat16x4x4_t b)
 
 /*
 **test_vld4q_lane_bf16:
-**     vld4.16 {d0\[2\], d2\[2\], d4\[2\], d6\[2\]}, \[r0\]
-**     bx      lr
+**     ...
+**     vld4.16 {d[0-9]+\[2\], d[0-9]+\[2\], d[0-9]+\[2\], d[0-9]+\[2\]}, \[r0\]
+**     ...
 */
 bfloat16x8x4_t
 test_vld4q_lane_bf16 (const bfloat16_t *a, bfloat16x8x4_t b)

diff --git a/gcc/testsuite/gcc.target/arm/simd/vmmla_1.c b/gcc/testsuite/gcc.target/arm/simd/vmmla_1.c
index fa512d905e2d473f596c67cef09fc1791fa30d25..aeb4a359e33513dbbd5ff3b9747c0ee7892d0942 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/simd/vmmla_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vmmla_1.c
@@ -1,6 +1,6 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_i8mm_ok } */
-/* { dg-options "-save-temps -O2 -march=armv8.2-a+i8mm" } */
+/* { dg-options "-save-temps -O2 -march=armv8.2-a+i8mm -mfloat-abi=hard" } */
 
 #include "arm_neon.h"