partition_desc=system.partition_desc
partition_desc_addr=133445976064
partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin
+power_model=Null
readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr=1099243192320
reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
+power_model=Null
ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
req_size=16
resp_size=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
p_state_clk_gate_min=2
pio_addr=134217728000
pio_latency=200
+power_model=Null
system=system
pio=system.iobus.master[14]
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
+power_model=Null
range=133446500352:133446508543
port=system.membus.master[5]
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
+power_model=Null
response_latency=2
use_default_range=false
width=16
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
pio_addr=0
pio_latency=200
pio_size=8
+power_model=Null
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
+power_model=Null
range=133429198848:133429207039
port=system.membus.master[4]
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
+power_model=Null
range=133445976064:133445984255
port=system.membus.master[6]
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
+power_model=Null
range=1048576:68157439
port=system.membus.master[7]
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
+power_model=Null
range=2147483648:2415919103
port=system.membus.master[8]
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
+power_model=Null
range=1099243192320:1099251580927
port=system.membus.master[3]
pio_addr=644245094400
pio_latency=200
pio_size=4294967296
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=549755813888
pio_latency=200
pio_size=4294967296
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=725849473024
pio_latency=200
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=725849473088
pio_latency=200
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=725849473152
pio_latency=200
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=725849473216
pio_latency=200
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=734439407616
pio_latency=200
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=734439407680
pio_latency=200
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=734439407744
pio_latency=200
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=734439407808
pio_latency=200
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=648540061696
pio_latency=200
pio_size=16384
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=1095216660480
pio_latency=200
pio_size=268435456
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
p_state_clk_gate_min=2
pio_addr=1099255906296
pio_latency=200
+power_model=Null
system=system
time=Thu Jan 1 00:00:00 2009
pio=system.membus.master[1]
pio_addr=1099255955456
pio_latency=200
platform=system.t1000
+power_model=Null
system=system
terminal=system.t1000.hterm
pio=system.iobus.master[13]
p_state_clk_gate_min=2
pio_latency=2
platform=system.t1000
+power_model=Null
system=system
pio=system.membus.master[0]
pio_addr=133412421632
pio_latency=200
platform=system.t1000
+power_model=Null
system=system
terminal=system.t1000.pterm
pio=system.iobus.master[12]
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.clk_domain",
+ "power_model": null,
"latency_var": 0,
"bandwidth": "0.000000",
"conf_table_reported": true,
"cxx_class": "Bridge",
"req_size": 16,
"clk_domain": "system.clk_domain",
+ "power_model": null,
"delay": 100,
"eventq_index": 0,
"master": {
"p_state_clk_gate_bins": 20,
"cxx_class": "NoncoherentXBar",
"clk_domain": "system.clk_domain",
+ "power_model": null,
"width": 16,
"eventq_index": 0,
"master": {
"cxx_class": "DumbTOD",
"pio_latency": 200,
"clk_domain": "system.clk_domain",
+ "power_model": null,
"system": "system",
"eventq_index": 0,
"time": "Thu Jan 1 00:00:00 2009",
"cxx_class": "Uart8250",
"pio_latency": 200,
"clk_domain": "system.clk_domain",
+ "power_model": null,
"system": "system",
"terminal": "system.t1000.pterm",
"platform": "system.t1000",
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.t1000.fake_membnks",
"ret_data16": 65535,
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.t1000.fake_jbi",
"ret_data16": 65535,
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.t1000.fake_l2esr_2",
"ret_data16": 65535,
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.t1000.fake_l2_4",
"ret_data16": 65535,
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.t1000.fake_l2_1",
"ret_data16": 65535,
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.t1000.fake_l2_2",
"ret_data16": 65535,
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.t1000.fake_l2_3",
"ret_data16": 65535,
"cxx_class": "Iob",
"pio_latency": 2,
"clk_domain": "system.clk_domain",
+ "power_model": null,
"system": "system",
"platform": "system.t1000",
"eventq_index": 0,
"cxx_class": "Uart8250",
"pio_latency": 200,
"clk_domain": "system.clk_domain",
+ "power_model": null,
"system": "system",
"terminal": "system.t1000.hterm",
"platform": "system.t1000",
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.t1000.fake_l2esr_3",
"ret_data16": 65535,
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.t1000.fake_ssi",
"ret_data16": 65535,
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.t1000.fake_l2esr_1",
"ret_data16": 65535,
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.t1000.fake_l2esr_4",
"ret_data16": 65535,
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.t1000.fake_clk",
"ret_data16": 65535,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.clk_domain",
+ "power_model": null,
"latency_var": 0,
"bandwidth": "0.000000",
"conf_table_reported": true,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.clk_domain",
+ "power_model": null,
"latency_var": 0,
"bandwidth": "0.000000",
"conf_table_reported": true,
"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
"p_state_clk_gate_min": 2,
+ "power_model": null,
"ret_data32": 4294967295,
"path": "system.membus.badaddr_responder",
"ret_data16": 65535,
},
"p_state_clk_gate_min": 2,
"snoop_filter": null,
+ "power_model": null,
"path": "system.membus",
"snoop_response_latency": 4,
"name": "membus",
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.clk_domain",
+ "power_model": null,
"latency_var": 0,
"bandwidth": "0.000000",
"conf_table_reported": true,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.clk_domain",
+ "power_model": null,
"latency_var": 0,
"bandwidth": "0.000000",
"conf_table_reported": true,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.clk_domain",
+ "power_model": null,
"latency_var": 0,
"bandwidth": "0.000000",
"conf_table_reported": true,
"in_addr_map": true
}
],
+ "power_model": null,
"work_cpus_ckpt_count": 0,
"thermal_components": [],
"path": "system",
"role": "MASTER"
},
"socket_id": 0,
+ "power_model": null,
"max_insts_all_threads": 0,
"path": "system.cpu",
"max_loads_any_thread": 0,
"cxx_class": "MmDisk",
"pio_latency": 200,
"clk_domain": "system.clk_domain",
+ "power_model": null,
"system": "system",
"eventq_index": 0,
"default_p_state": "UNDEFINED",