This commit introduces the nps400 machine type as a variant of arc.
There's a new flag in the assembler to select this machine type. All
other changes are just adding handling of the new machine type into the
relevant places.
The nps400 is an arc700 variant with some vendor specific instructions
added into the instruction set. This commit does not add any of the new
instructions, this is just laying the groundwork for future commits.
However, in preparation for these new instructions a new opcode define for
nps400 has been added to include/opcode/arc.h, this new opcode define is
used in the assembler and disassembler along with the existing define
for arc700 such that when assembling and disassembling for nps400 the
user will have access to all arc700 instructions and all the nps400
vendor extension instructions.
bfd/ChangeLog:
* archures.c (bfd_mach_arc_nps400): Define.
* bfd-in2.h: Regenerate.
* cpu-arc.c (arch_info_struct): New entry for nps400, renumber
some existing entries to make space.
* elf32-arc.c (arc_elf_object_p): Add nps400 case.
(arc_elf_final_write_processing): Likewise.
binutils/ChangeLog:
* readelf.c (decode_ARC_machine_flags): Handle nps400.
gas/ChangeLog:
* config/tc-arc.c (cpu_types): Add nps400 entry.
(check_zol): Handle nps400.
include/ChangeLog:
* elf/arc.h (E_ARC_MACH_NPS400): Define.
* opcode/arc.h (ARC_OPCODE_NPS400): Define.
opcodes/ChangeLog:
* arc-dis.c (print_insn_arc): Handle nps400.
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * archures.c (bfd_mach_arc_nps400): Define.
+ * bfd-in2.h: Regenerate.
+ * cpu-arc.c (arch_info_struct): New entry for nps400, renumber
+ some existing entries to make space.
+ * elf32-arc.c (arc_elf_object_p): Add nps400 case.
+ (arc_elf_final_write_processing): Likewise.
+
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
.#define bfd_mach_arc_arc601 4
.#define bfd_mach_arc_arc700 3
.#define bfd_mach_arc_arcv2 5
+.#define bfd_mach_arc_nps400 6
. bfd_arch_m32c, {* Renesas M16C/M32C. *}
.#define bfd_mach_m16c 0x75
.#define bfd_mach_m32c 0x78
#define bfd_mach_arc_arc601 4
#define bfd_mach_arc_arc700 3
#define bfd_mach_arc_arcv2 5
+#define bfd_mach_arc_nps400 6
bfd_arch_m32c, /* Renesas M16C/M32C. */
#define bfd_mach_m16c 0x75
#define bfd_mach_m32c 0x78
ARC (bfd_mach_arc_arc601, "ARC601", FALSE, &arch_info_struct[3]),
ARC (bfd_mach_arc_arc700, "ARC700", FALSE, &arch_info_struct[4]),
ARC (bfd_mach_arc_arc700, "A7", FALSE, &arch_info_struct[5]),
- ARC (bfd_mach_arc_arcv2, "ARCv2", FALSE, &arch_info_struct[6]),
- ARC (bfd_mach_arc_arcv2, "EM", FALSE, &arch_info_struct[7]),
+ ARC (bfd_mach_arc_nps400, "NPS400", FALSE, &arch_info_struct[6]),
+ ARC (bfd_mach_arc_arcv2, "ARCv2", FALSE, &arch_info_struct[7]),
+ ARC (bfd_mach_arc_arcv2, "EM", FALSE, &arch_info_struct[8]),
ARC (bfd_mach_arc_arcv2, "HS", FALSE, NULL),
};
case E_ARC_MACH_ARC700:
mach = bfd_mach_arc_arc700;
break;
+ case E_ARC_MACH_NPS400:
+ mach = bfd_mach_arc_nps400;
+ break;
case EF_ARC_CPU_ARCV2HS:
case EF_ARC_CPU_ARCV2EM:
mach = bfd_mach_arc_arcv2;
case bfd_mach_arc_arc700:
emf = EM_ARC_COMPACT;
break;
+ case bfd_mach_arc_nps400:
+ emf = EM_ARC_COMPACT;
+ break;
case bfd_mach_arc_arcv2:
emf = EM_ARC_COMPACT2;
break;
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * readelf.c (decode_ARC_machine_flags): Handle nps400.
+
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* readelf.c (get_machine_flags): Move arc processing into...
case E_ARC_MACH_ARC700:
strcat (buf, ", ARC700");
break;
+ case E_ARC_MACH_NPS400:
+ strcat (buf, ", NPS400");
+ break;
/* The only times we should end up here are (a) A corrupt ELF, (b) A
new ELF with new architecture being read by an old version of
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-arc.c (cpu_types): Add nps400 entry.
+ (check_zol): Handle nps400.
+
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_select_cpu): Remove use of
E_ARC_MACH_ARC600, 0x00},
{ "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
E_ARC_MACH_ARC700, 0x00},
+ { "nps400", ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400, bfd_mach_arc_nps400,
+ E_ARC_MACH_NPS400, 0x00},
{ "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
EF_ARC_CPU_ARCV2EM, ARC_CD},
{ "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
end of the ZOL label @%s"), S_GET_NAME (s));
/* Fall through. */
+ case bfd_mach_arc_nps400:
case bfd_mach_arc_arc700:
if (arc_last_insns[0].has_delay_slot)
as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * elf/arc.h (E_ARC_MACH_NPS400): Define.
+ * opcode/arc.h (ARC_OPCODE_NPS400): Define.
+
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
#define E_ARC_MACH_ARC600 0x00000002
#define E_ARC_MACH_ARC601 0x00000004
#define E_ARC_MACH_ARC700 0x00000003
+#define E_ARC_MACH_NPS400 0x00000007
#define EF_ARC_CPU_ARCV2EM 0x00000005
#define EF_ARC_CPU_ARCV2HS 0x00000006
#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
+#define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */
/* CPU extensions. */
#define ARC_EA 0x0001
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-dis.c (print_insn_arc): Handle nps400.
+
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
* arc-opc.c (BASE): Delete.
switch (info->mach)
{
+ case bfd_mach_arc_nps400:
+ isa_mask = ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400;
+ break;
+
case bfd_mach_arc_arc700:
isa_mask = ARC_OPCODE_ARC700;
break;