[xcc, sim] moved shamt field and renamed shifts

diff --git a/riscv/decode.h b/riscv/decode.h
index ddf4eca0791227c5a74aaf16f1d92cadd770195e..627502ee3efa190b2a4ae4c732a11ed7c8c9fb70 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -26,6 +26,7 @@ const int IMM_BITS = 12;
 const int TARGET_BITS = 27;
 const int SHAMT_BITS = 6;
 const int FUNCT_BITS = 3;
+const int FUNCTR_BITS = 7;
 const int FFUNCT_BITS = 5;
 const int BIGIMM_BITS = 20;
 const int BRANCH_ALIGN_BITS = 1;
@@ -93,8 +94,7 @@ struct jtype_t
 struct rtype_t
 {
   unsigned rc : GPRID_BITS;
-  unsigned shamt : SHAMT_BITS;
-  unsigned unused : 1;
+  unsigned functr : FUNCTR_BITS;
   unsigned funct : FUNCT_BITS;
   unsigned rb : GPRID_BITS;
   unsigned ra : GPRID_BITS;
@@ -139,7 +139,8 @@ union insn_t
 #define BIGIMM insn.btype.bigimm
 #define IMM insn.itype.imm
 #define SIMM ((int32_t)((uint32_t)insn.itype.imm<<(32-IMM_BITS))>>(32-IMM_BITS))
-#define SHAMT insn.rtype.shamt
+#define SHAMT (insn.itype.imm & 0x3F)
+#define SHAMTW (insn.itype.imm & 0x1F)
 #define TARGET insn.jtype.target
 #define BRANCH_TARGET (npc + (SIMM << BRANCH_ALIGN_BITS))
 #define JUMP_TARGET ((npc & ~((1<<(TARGET_BITS+JUMP_ALIGN_BITS))-1)) + (TARGET << JUMP_ALIGN_BITS))

diff --git a/riscv/execute.h b/riscv/execute.h
index ae2511f753a89fcda682edf0e9a3bc838401ae02..f1374b5483453a2cdb5101591ebffd8d34795a63 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -474,31 +474,50 @@ switch((insn.bits >> 0x19) & 0x7f)
         #include "insns/addi.h"
         break;
       }
-      case 0x1:
+      case 0x2:
       {
         #include "insns/slti.h"
         break;
       }
-      case 0x2:
+      case 0x3:
       {
         #include "insns/sltiu.h"
         break;
       }
-      case 0x3:
+      case 0x4:
       {
         #include "insns/andi.h"
         break;
       }
-      case 0x4:
+      case 0x5:
       {
         #include "insns/ori.h"
         break;
       }
-      case 0x5:
+      case 0x6:
       {
         #include "insns/xori.h"
         break;
       }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe007fc0) == 0xe8007080)
+        {
+          #include "insns/srli.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fc0) == 0xe80070c0)
+        {
+          #include "insns/srai.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fc0) == 0xe8007040)
+        {
+          #include "insns/slli.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
       default:
       {
         #include "insns/unimp.h"
@@ -512,14 +531,14 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007fe0) == 0xea0000e0)
+        if((insn.bits & 0xfe007fe0) == 0xea000000)
         {
-          #include "insns/nor.h"
+          #include "insns/add.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea000060)
+        if((insn.bits & 0xfe007fe0) == 0xea0000e0)
         {
-          #include "insns/sltu.h"
+          #include "insns/nor.h"
           break;
         }
         if((insn.bits & 0xfe007fe0) == 0xea0000c0)
@@ -537,14 +556,14 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/or.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea000000)
+        if((insn.bits & 0xfe007fe0) == 0xea000040)
         {
-          #include "insns/add.h"
+          #include "insns/slt.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea000040)
+        if((insn.bits & 0xfe007fe0) == 0xea000060)
         {
-          #include "insns/slt.h"
+          #include "insns/sltu.h"
           break;
         }
         if((insn.bits & 0xfe007fe0) == 0xea000080)
@@ -593,52 +612,25 @@ switch((insn.bits >> 0x19) & 0x7f)
         }
         #include "insns/unimp.h"
       }
-      case 0x4:
+      case 0x7:
       {
-        if((insn.bits & 0xfe007fe0) == 0xea004040)
+        if((insn.bits & 0xfe007fe0) == 0xea007080)
         {
           #include "insns/srlv.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea004060)
+        if((insn.bits & 0xfe007fe0) == 0xea0070c0)
         {
           #include "insns/srav.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea004020)
+        if((insn.bits & 0xfe007fe0) == 0xea007040)
         {
           #include "insns/sllv.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x5:
-      {
-        if((insn.bits & 0xfff07800) == 0xea005000)
-        {
-          #include "insns/sll.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x6:
-      {
-        if((insn.bits & 0xfff07800) == 0xea006000)
-        {
-          #include "insns/srl.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x7:
-      {
-        if((insn.bits & 0xfff07800) == 0xea007000)
-        {
-          #include "insns/sra.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
       default:
       {
         #include "insns/unimp.h"
@@ -655,6 +647,25 @@ switch((insn.bits >> 0x19) & 0x7f)
         #include "insns/addiw.h"
         break;
       }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xec007040)
+        {
+          #include "insns/slliw.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec007080)
+        {
+          #include "insns/srliw.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec0070c0)
+        {
+          #include "insns/sraiw.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
       default:
       {
         #include "insns/unimp.h"
@@ -719,52 +730,25 @@ switch((insn.bits >> 0x19) & 0x7f)
         }
         #include "insns/unimp.h"
       }
-      case 0x4:
+      case 0x7:
       {
-        if((insn.bits & 0xfe007fe0) == 0xee004060)
+        if((insn.bits & 0xfe007fe0) == 0xee0070c0)
         {
           #include "insns/sravw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee004020)
+        if((insn.bits & 0xfe007fe0) == 0xee007040)
         {
           #include "insns/sllvw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee004040)
+        if((insn.bits & 0xfe007fe0) == 0xee007080)
         {
           #include "insns/srlvw.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x5:
-      {
-        if((insn.bits & 0xfff07c00) == 0xee005000)
-        {
-          #include "insns/sllw.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x6:
-      {
-        if((insn.bits & 0xfff07c00) == 0xee006000)
-        {
-          #include "insns/srlw.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x7:
-      {
-        if((insn.bits & 0xfff07c00) == 0xee007000)
-        {
-          #include "insns/sraw.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
       default:
       {
         #include "insns/unimp.h"

diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
deleted file mode 100644 (file)
index a07e038..0000000
--- a/riscv/insns/sll.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RB << SHAMT;

diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
new file mode 100644 (file)
index 0000000..606512b
--- /dev/null
+++ b/riscv/insns/slli.h
@@ -0,0 +1,2 @@
+require64;
+RA = RB << SHAMT;

diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h
new file mode 100644 (file)
index 0000000..c8b345c
--- /dev/null
+++ b/riscv/insns/slliw.h
@@ -0,0 +1 @@
+RA = sext32(RB << SHAMTW);

diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
deleted file mode 100644 (file)
index 67e6809..0000000
--- a/riscv/insns/sllw.h
+++ /dev/null
@@ -1 +0,0 @@
-RC = sext32(RB << SHAMT);

diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
deleted file mode 100644 (file)
index 19118f0..0000000
--- a/riscv/insns/sra.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = sreg_t(RB) >> SHAMT;

diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
new file mode 100644 (file)
index 0000000..12a67a3
--- /dev/null
+++ b/riscv/insns/srai.h
@@ -0,0 +1,2 @@
+require64;
+RA = sreg_t(RB) >> SHAMT;

diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
new file mode 100644 (file)
index 0000000..7289347
--- /dev/null
+++ b/riscv/insns/sraiw.h
@@ -0,0 +1 @@
+RA = sext32(sreg_t(RB) >> SHAMTW);

diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
deleted file mode 100644 (file)
index c2decb9..0000000
--- a/riscv/insns/sraw.h
+++ /dev/null
@@ -1 +0,0 @@
-RC = sext32(sreg_t(RB) >> SHAMT);

diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
deleted file mode 100644 (file)
index 47426b1..0000000
--- a/riscv/insns/srl.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RB >> SHAMT;

diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h
new file mode 100644 (file)
index 0000000..d7bc2b4
--- /dev/null
+++ b/riscv/insns/srli.h
@@ -0,0 +1,2 @@
+require64;
+RA = RB >> SHAMT;

diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h
new file mode 100644 (file)
index 0000000..6534a89
--- /dev/null
+++ b/riscv/insns/srliw.h
@@ -0,0 +1 @@
+RA = sext32((uint32_t)RB >> SHAMTW);

diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
deleted file mode 100644 (file)
index 9e41c8c..0000000
--- a/riscv/insns/srlw.h
+++ /dev/null
@@ -1 +0,0 @@
-RC = sext32((uint32_t)RB >> SHAMT);