whitespace cleanup

diff --git a/openpower/isa/fixedstoreshift.mdwn b/openpower/isa/fixedstoreshift.mdwn
index 91f1f11851836c613a3f4f8aba22067771fa9e5a..3b04b75c63cab88fbb23b38e14e11b3a89b5d918 100644 (file)
--- a/openpower/isa/fixedstoreshift.mdwn
+++ b/openpower/isa/fixedstoreshift.mdwn
@@ -237,12 +237,10 @@ Description:
 
     Let the effective address (EA) be the sum of the contents of
     register RB shifted by (SH+1), and (RA|0).
-    (RS)56:63 are stored into bits 0:7 of the
-    halfword in storage addressed by EA. (RS) 48:55 are
-    stored into bits 8:15 of the halfword in storage
 
-    (RS)[48:55] are stored into bits 8:15 of the halfword in storage
-    addressed by EA.
+    (RS)56:63 are stored into bits 0:7 of the halfword in storage
+    addressed by EA.  (RS)[48:55] are stored into bits 8:15 of
+    the halfword in storage addressed by EA.
 
 Special Registers Altered:
 
@@ -269,7 +267,6 @@ Description:
     (RS)[56:63] are stored into bits 0:7 of the
     word in storage addressed by EA. (RS) [48:55] are stored
     into bits 8:15 of the word in storage addressed by EA.
-
     (RS)[40:47] are stored into bits 16:23 of the word in stor-
     age addressed by EA. (RS) [32:39] are stored into bits
     24:31 of the word in storage addressed by EA.