Make return value of $clog2 signed

As per Verilog 2005 - 17.11.1.

Fixes #708

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index bb4c9735de8b9cabccc89805e7411cc73d11ca1d..55abe165f87b012d13426546f40cb85e8b54d4df 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1913,7 +1913,7 @@ skip_dynamic_range_lvalue_expansion:;
                                        if (arg_value.bits.at(i) == RTLIL::State::S1)
                                                result = i + 1;
 
-                               newNode = mkconst_int(result, false);
+                               newNode = mkconst_int(result, true);
                                goto apply_newNode;
                        }