Set init values for wrapped async control signals

diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index f37e07a8977c069167f2ebb6e2804b17029e73ab..bc18bbbd6adf35f68dee357a2940b166839d630f 100644 (file)
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -44,6 +44,7 @@ struct Clk2fflogicPass : public Pass {
        }
        SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity, IdString past_sig_id) {
                Wire *past_sig = module->addWire(past_sig_id, GetSize(sig));
+               past_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S0 : State::S1, GetSize(sig));
                module->addFf(NEW_ID, sig, past_sig);
                if (polarity)
                        sig = module->Or(NEW_ID, sig, past_sig);
@@ -56,6 +57,7 @@ struct Clk2fflogicPass : public Pass {
        }
        SigSpec wrap_async_control_gate(Module *module, SigSpec sig, bool polarity) {
                Wire *past_sig = module->addWire(NEW_ID);
+               past_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S0 : State::S1, GetSize(sig));
                module->addFfGate(NEW_ID, sig, past_sig);
                if (polarity)
                        sig = module->OrGate(NEW_ID, sig, past_sig);