turnip: split up gmem/tile alignment
authorJonathan Marek <jonathan@marek.ca>
Tue, 18 Feb 2020 13:54:15 +0000 (08:54 -0500)
committerMarge Bot <eric+marge@anholt.net>
Thu, 9 Apr 2020 14:43:02 +0000 (14:43 +0000)
Note: the x1/y1 align in tu6_emit_blit_scissor was broken

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>

src/freedreno/vulkan/tu_cmd_buffer.c
src/freedreno/vulkan/tu_device.c
src/freedreno/vulkan/tu_pass.c
src/freedreno/vulkan/tu_private.h

index f20019a1b302e9d473685d13d295b40adc9c28dc..3921da2451c78dd31ea404ef188639cae2cc88c4 100644 (file)
@@ -123,7 +123,6 @@ force_sysmem(const struct tu_cmd_buffer *cmd,
              const struct VkRect2D *render_area)
 {
    const struct tu_framebuffer *fb = cmd->state.framebuffer;
-   const struct tu_physical_device *device = cmd->device->physical_device;
    bool has_linear_mipmapped_store = false;
    const struct tu_render_pass *pass = cmd->state.pass;
 
@@ -170,7 +169,7 @@ force_sysmem(const struct tu_cmd_buffer *cmd,
     * work around this, we force-enable sysmem rendering.
     */
    const uint32_t y2 = render_area->offset.y + render_area->extent.height;
-   const uint32_t aligned_y2 = ALIGN_POT(y2, device->tile_align_h);
+   const uint32_t aligned_y2 = ALIGN_POT(y2, GMEM_ALIGN_H);
 
    return has_linear_mipmapped_store && aligned_y2 > fb->height;
 }
@@ -180,9 +179,9 @@ tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
                                     const struct tu_device *dev,
                                     uint32_t pixels)
 {
-   const uint32_t tile_align_w = dev->physical_device->tile_align_w;
-   const uint32_t tile_align_h = dev->physical_device->tile_align_h;
-   const uint32_t max_tile_width = 1024; /* A6xx */
+   const uint32_t tile_align_w = 64; /* note: 32 when no input attachments */
+   const uint32_t tile_align_h = 16;
+   const uint32_t max_tile_width = 1024;
 
    /* note: don't offset the tiling config by render_area.offset,
     * because binning pass can't deal with it
@@ -670,12 +669,11 @@ tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
    uint32_t x2 = x1 + render_area->extent.width - 1;
    uint32_t y2 = y1 + render_area->extent.height - 1;
 
-   /* TODO: alignment requirement seems to be less than tile_align_w/h */
    if (align) {
-      x1 = x1 & ~cmd->device->physical_device->tile_align_w;
-      y1 = y1 & ~cmd->device->physical_device->tile_align_h;
-      x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
-      y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
+      x1 = x1 & ~(GMEM_ALIGN_W - 1);
+      y1 = y1 & ~(GMEM_ALIGN_H - 1);
+      x2 = ALIGN_POT(x2 + 1, GMEM_ALIGN_W) - 1;
+      y2 = ALIGN_POT(y2 + 1, GMEM_ALIGN_H) - 1;
    }
 
    tu_cs_emit_regs(cs,
index e908fc0a8624190c1cba972c278b8774a0fe3a61..ffadb3ce6b99a63ec0bfabea429c9590aeb68c41 100644 (file)
@@ -265,8 +265,6 @@ tu_physical_device_init(struct tu_physical_device *device,
 
    switch (device->gpu_id) {
    case 618:
-      device->tile_align_w = 64;
-      device->tile_align_h = 16;
       device->magic.RB_UNKNOWN_8E04_blit = 0x00100000;
       device->ccu_offset_gmem = 0x7c000; /* 0x7e000 in some cases? */
       device->ccu_offset_bypass = 0x10000;
@@ -275,8 +273,6 @@ tu_physical_device_init(struct tu_physical_device *device,
       break;
    case 630:
    case 640:
-      device->tile_align_w = 64;
-      device->tile_align_h = 16;
       device->magic.RB_UNKNOWN_8E04_blit = 0x01000000;
       device->ccu_offset_gmem = 0xf8000;
       device->ccu_offset_bypass = 0x20000;
index 26ce2b4958f7efd872322d60779b3eec2dd23db8..dd792762822f63e960affe4d8250ebce275e6c9e 100644 (file)
@@ -360,8 +360,6 @@ tu_GetRenderAreaGranularity(VkDevice _device,
                             VkRenderPass renderPass,
                             VkExtent2D *pGranularity)
 {
-   TU_FROM_HANDLE(tu_device, device, _device);
-
-   pGranularity->width = device->physical_device->tile_align_w;
-   pGranularity->height = device->physical_device->tile_align_h;
+   pGranularity->width = GMEM_ALIGN_W;
+   pGranularity->height = GMEM_ALIGN_H;
 }
index 4378406eb93de18e05c3ef3d8bcd7735eb6efa29..1c4f978029d892a4f745095cf432613d53b531e9 100644 (file)
@@ -314,10 +314,10 @@ struct tu_physical_device
    unsigned gpu_id;
    uint32_t gmem_size;
    uint64_t gmem_base;
-   uint32_t tile_align_w;
-   uint32_t tile_align_h;
    uint32_t ccu_offset_gmem;
    uint32_t ccu_offset_bypass;
+#define GMEM_ALIGN_W 16
+#define GMEM_ALIGN_H 4
 
    struct {
       uint32_t RB_UNKNOWN_8E04_blit;    /* for CP_BLIT's */