targets: pass speedgrade to S7PLL/S7MMCM

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 8056109076af947ef60866726d91ff6b43509a9e..98d45c65181d487aa6cf884a54faa9e9cae26181 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -25,7 +25,7 @@ class _CRG(Module):
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
 
-        self.submodules.pll = pll = S7PLL()
+        self.submodules.pll = pll = S7PLL(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 91df0d384cb0f9078954892dedec9f7128c8c0cb..663eaf0b6fb6fd8973317ba036b63319fe9852ba 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -24,7 +24,7 @@ class _CRG(Module):
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
 
-        self.submodules.pll = pll = S7MMCM()
+        self.submodules.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 10078b30075cbf3325ef7327ce4ed4e701a76468..c2f94e5a90b6a63603896cc72080a6eaf4749be9 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -24,7 +24,7 @@ class _CRG(Module):
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
 
-        self.submodules.pll = pll = S7MMCM()
+        self.submodules.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index fb863e716414e65c4998042ab3b63fff4dd2e8e1..72c5e8963d3a73f1a0afa3c8c3b7444237c37bcf 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -23,7 +23,7 @@ class _CRG(Module):
         self.clock_domains.cd_clk200 = ClockDomain()
         self.clock_domains.cd_clk100 = ClockDomain()
 
-        self.submodules.pll = pll = S7MMCM()
+        self.submodules.pll = pll = S7MMCM(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 9ce1719d91d98949de25098c13135b0bfdeadf86..ca485774f693d3678ddb355e0db22de313582c73 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -26,7 +26,7 @@ class _CRG(Module):
         self.clock_domains.cd_clk200 = ClockDomain()
         self.clock_domains.cd_clk100 = ClockDomain()
 
-        self.submodules.pll = pll = S7MMCM()
+        self.submodules.pll = pll = S7MMCM(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)