(no commit message)

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index f1e9f38cd0aba905840f5eb9ec2f4f3550ef4171..c9f2f37a7dc135e8bd3efb3fb73dffd8591efda5 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -71,7 +71,7 @@ CW2-Form
 ```
     creg = CR[4*BFA+32:4*BFA+35]
     result = (¬fmap ^ creg) & fmsk
-    RT[60:63] = result # MSB0 numbering, 63 is LSB
+    RT = [0] * 60 || result
     If Rc:
         CR0 = analyse(RT)
 ```
@@ -113,6 +113,12 @@ Mode capability
 Hardware Architectural Note: when M=1 this instruction is a Read-Modify-Write
 on the `BF` CR Field. When M=0 it is a more normal Write.
 
+Special Registers Altered:
+
+```
+    CR Field BF
+```
+
 ## mtcrweird
 
 CW-Form
@@ -145,6 +151,12 @@ When used with SVP64 Prefixing this is a [[sv/cr_ops]] SVP64
 type operation that has 3-bit Data-dependent and 3-bit Predicate-result
 capability (BF is 3 bits)
 
+Special Registers Altered:
+
+```
+    CR Field BF
+```
+
 ## mcrfm - Move CR Field, masked.
 
 CW-Form
@@ -189,6 +201,12 @@ to BF by ensuring that `fmsk` and `fmap` have the same bit set.  Also,
 individual bits in BF may be set to 1 by ensuring that the required bit of
 `fmsk` is set to zero and the same bit in `fmap` is set to 1*
 
+Special Registers Altered:
+
+```
+    CR Field BF
+```
+
 ## crweirder
 
 ```
@@ -205,6 +223,12 @@ individual bits in BF may be set to 1 by ensuring that the required bit of
     CR[32+BT] = result
 ```
 
+Special Registers Altered:
+
+```
+    CR[BT+32]
+```
+
 When used with SVP64 Prefixing this is a [[sv/cr_ops]] SVP64
 type operation that has 5-bit Data-dependent
 capability (BT is 5 bits)