Fix test for counter

diff --git a/tests/ice40/counter.ys b/tests/ice40/counter.ys
index fb32e67a5df76eeab6e4cbebe8f32c0f4d690677..c65c21622bcdfba16187e7468c35183ff6f6bd70 100644 (file)
--- a/tests/ice40/counter.ys
+++ b/tests/ice40/counter.ys
@@ -5,7 +5,7 @@ flatten
 equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 7 t:SB_CARRY
+select -assert-count 6 t:SB_CARRY
 select -assert-count 8 t:SB_DFFR
 select -assert-count 8 t:SB_LUT4
 select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D