radv: Don't emit cache flushes on subpass switch.

I think we should only flush right before an action (draw/dispatch etc.),
as otherwise it is too easy to issue redundant flushes.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 274495f134f3acbb7841922da8535cae7b02d5a0..10c51427679de28d15227e41e97eb328bedea3a8 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2265,8 +2265,6 @@ void radv_CmdBeginRenderPass(
        cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
        radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
 
-       si_emit_cache_flush(cmd_buffer);
-
        radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
        assert(cmd_buffer->cs->cdw <= cdw_max);
 
@@ -2279,7 +2277,6 @@ void radv_CmdNextSubpass(
 {
        RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
 
-       si_emit_cache_flush(cmd_buffer);
        radv_cmd_buffer_resolve_subpass(cmd_buffer);
 
        radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
@@ -2704,7 +2701,6 @@ void radv_CmdEndRenderPass(
 
        radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
 
-       si_emit_cache_flush(cmd_buffer);
        radv_cmd_buffer_resolve_subpass(cmd_buffer);
 
        for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {

diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index ffaa9a3d5e82ea827398f9fe759f48a006cd4ecf..8009b287c4db422099415b83c0bd6f30017c79a9 100644 (file)
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -405,7 +405,6 @@ emit_fast_clear_flush(struct radv_cmd_buffer *cmd_buffer,
        radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
        cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
                                         RADV_CMD_FLAG_FLUSH_AND_INV_CB_META);
-       si_emit_cache_flush(cmd_buffer);
 }
 
 /**

diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c
index 288a1479debecba7dbc4998baa23a135c3b45247..105270cb74219ee1dd9217efc0da23602303fdb1 100644 (file)
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -364,7 +364,6 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
 
        radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
        cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
-       si_emit_cache_flush(cmd_buffer);
 }
 
 void radv_CmdResolveImage(