soc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped).

diff --git a/litex/soc/cores/spi_flash.py b/litex/soc/cores/spi_flash.py
index 0ed073dea0492267c268d85900146af96622c2a2..906ffb136925a4631f877de49a7bedca1da8ff4c 100644 (file)
--- a/litex/soc/cores/spi_flash.py
+++ b/litex/soc/cores/spi_flash.py
@@ -365,3 +365,24 @@ class S7SPIFlash(Module, AutoCSR):
             pads.mosi.eq(spi.pads.mosi),
             spi.pads.miso.eq(pads.miso)
         ]
+
+
+# Lattice ECP5 FPGAs SPI Flash (non-memory-mapped) -------------------------------------------------
+
+class ECP5SPIFlash(Module, AutoCSR):
+    def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6):
+        self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq)
+        self.specials += Instance("USRMCLK",
+            i_USRMCLKI  = spi.pads.clk,
+            i_USRMCLKTS = 0
+        )
+        if hasattr(pads, "vpp"):
+            pads.vpp.reset = 1
+        if hasattr(pads, "hold"):
+            pads.hold.reset = 1
+        if hasattr(pads, "cs_n"):
+            self.comb += pads.cs_n.eq(spi.pads.cs_n)
+        self.comb += [
+            pads.mosi.eq(spi.pads.mosi),
+            spi.pads.miso.eq(pads.miso)
+        ]