uart2wishbone: add default baudrate

diff --git a/miscope/host/uart2wishbone.py b/miscope/host/uart2wishbone.py
index df79a1a1282f415568bb1466aebd3c9db664856f..ebed0614905fb9a6a08643303824d851d6f536cb 100644 (file)
--- a/miscope/host/uart2wishbone.py
+++ b/miscope/host/uart2wishbone.py
@@ -10,9 +10,9 @@ def write_b(uart, data):
 class Uart2Wishbone:
        WRITE_CMD  = 0x01
        READ_CMD   = 0x02
-       def __init__(self, port, baudrate, addrmap=None, debug=False):
+       def __init__(self, port, baudrate=115200, addrmap=None, debug=False):
                self.port = port
-               self.baudrate = baudrate
+               self.baudrate = str(baudrate)
                self.debug = debug
                self.uart = serial.Serial(port, baudrate, timeout=0.25)
                self.regs = build_map(addrmap, self.read, self.write)

diff --git a/miscope/uart2wishbone.py b/miscope/uart2wishbone.py
index 4fce7738535f5282465eceb6823577ef961e4837..b6665e87cab5574cc168801f0ae1909b14f89094 100644 (file)
--- a/miscope/uart2wishbone.py
+++ b/miscope/uart2wishbone.py
@@ -161,7 +161,7 @@ class UARTMux(Module):
 class UART2Wishbone(Module, AutoCSR):
        WRITE_CMD = 0x01
        READ_CMD = 0x02
-       def __init__(self, pads, clk_freq, baud, share_uart=False):
+       def __init__(self, pads, clk_freq, baud=115200, share_uart=False):
                
                # Wishbone interface
                self.wishbone = wishbone.Interface()