from migen.sim.icarus import Runner
from migen.bus.transactions import *
-import sys
-sys.path.append("../")
-
-from migScope import recorder
-
+from miscope import recorder
arm_done = False
trig_dat = 0
from migen.sim.icarus import Runner
from migen.bus.transactions import *
-import sys
-sys.path.append("../")
-
-from migScope import trigger
-
-from migScope.tools.truthtable import *
+from miscope import trigger
+from miscope.tools.truthtable import *
def term_prog(off, dat):
for i in range(4):
+++ /dev/null
-from migen.fhdl.structure import *
-from migen.fhdl import verilog, autofragment
-from migen.bus import csr
-from migen.sim.generic import Simulator, PureSimulable, TopLevel
-from migen.sim.icarus import Runner
-from migen.bus.transactions import *
-
-import sys
-sys.path.append("../")
-
-from migScope import trigger, recorder
-from migScope.tools.truthtable import *
-from migScope.tools.vcd import *
-
-TRIGGER_ADDR = 0x0000
-RECORDER_ADDR = 0x0200
-
-rec_done = False
-dat_rdy = False
-
-dat_vcd = []
-
-def term_prog(off, dat):
- for i in range(4):
- yield TWrite(off+3-i, (dat>>(8*i))&0xFF)
-
-
-def sum_prog(off, addr, dat):
- we = 2
- yield TWrite(off+3, addr%0xFF)
- yield TWrite(off+2, (addr>>8)%0xFF)
- yield TWrite(off+1, we+dat)
- yield TWrite(off+0, 0)
- for i in range(4):
- yield TWrite(off+i,0)
-
-def csr_transactions(trigger0, recorder0):
-
- # Trigger Prog
- ##############################
-
- # Term Prog
- term_trans = []
- term_trans += [term_prog(trigger0.ports[0].reg_base, 0x00000000)]
- term_trans += [term_prog(trigger0.ports[1].reg_base, 0x00000004)]
- term_trans += [term_prog(trigger0.ports[2].reg_base, 0x00000008)]
- term_trans += [term_prog(trigger0.ports[3].reg_base, 0x0000000C)]
- for t in term_trans:
- for r in t:
- yield r
-
- # Sum Prog
- sum_tt = gen_truth_table("term0 | term1 | term2 | term3")
- sum_trans = []
- for i in range(len(sum_tt)):
- sum_trans.append(sum_prog(trigger0.sum.reg_base, i, sum_tt[i]))
- for t in sum_trans:
- for r in t:
- yield r
-
- # Recorder Prog
- ##############################
- #Reset
- yield TWrite(recorder0.address + 0, 1)
- yield TWrite(recorder0.address + 0, 0)
-
- #Size
- yield TWrite(recorder0.address + 3, 0)
- yield TWrite(recorder0.address + 4, 64)
-
- #Offset
- yield TWrite(recorder0.address + 5, 0)
- yield TWrite(recorder0.address + 6, 16)
-
- #Arm
- yield TWrite(recorder0.address + 1, 1)
-
- # Wait Record to be done
- ##############################
- global rec_done
- while not rec_done:
- yield None
-
- # Read recorded data
- ##############################
- global dat_rdy
- for t in range(64):
- yield TWrite(recorder0.address + 7, 1)
- dat_rdy = False
- yield TWrite(recorder0.address + 7, 0)
- yield TRead(recorder0.address + 8)
- yield TRead(recorder0.address + 9)
- yield TRead(recorder0.address + 10)
- yield TRead(recorder0.address + 11)
- dat_rdy = True
-
- dat_rdy = False
-
- for t in range(512):
- yield None
-
-
-trig_sig_val = 0
-
-
-def main():
-
- # Trigger
- term0 = trigger.Term(32)
- term1 = trigger.Term(32)
- term2 = trigger.Term(32)
- term3 = trigger.Term(32)
- trigger0 = trigger.Trigger(TRIGGER_ADDR, 32, 64, [term0, term1, term2, term3])
-
- # Recorder
- recorder0 = recorder.Recorder(RECORDER_ADDR, 32, 1024)
-
- # Csr Master
- csr_master0 = csr.Initiator(csr_transactions(trigger0, recorder0))
-
- # Csr Interconnect
- csrcon0 = csr.Interconnect(csr_master0.bus,
- [
- trigger0.bank.interface,
- recorder0.bank.interface
- ])
-
- trig_sig = Signal(32)
- comb = []
- comb +=[
- trigger0.in_trig.eq(trig_sig)
- ]
-
- comb += [
- recorder0.trig_dat.eq(trig_sig),
- recorder0.trig_hit.eq(trigger0.hit)
- ]
- # Term Test
- def term_stimuli(s):
- global trig_sig_val
- s.wr(trig_sig,trig_sig_val)
- trig_sig_val += 1
- trig_sig_val = trig_sig_val % 256
-
- # Recorder Data
- def recorder_data(s):
- global rec_done
- if s.rd(recorder0.sequencer.rec_done) == 1:
- rec_done = True
-
- global dat_rdy
- if dat_rdy:
- print("%08X" %s.rd(recorder0._get_dat.field.w))
- global dat_vcd
- dat_vcd.append(s.rd(recorder0._get_dat.field.w))
-
-
- # Simulation
- def end_simulation(s):
- s.interrupt = csr_master0.done
- myvcd = Vcd()
- myvcd.add(Var("wire", 32, "trig_dat", dat_vcd))
- f = open("tb_Miscope_Out.vcd", "w")
- f.write(str(myvcd))
- f.close()
-
-
- fragment = autofragment.from_local()
- fragment += Fragment(comb=comb)
- fragment += Fragment(sim=[term_stimuli])
- fragment += Fragment(sim=[recorder_data])
- fragment += Fragment(sim=[end_simulation])
-
- sim = Simulator(fragment, Runner(),TopLevel("tb_MigScope.vcd"))
- sim.run(2000)
-
-main()
-input()
--- /dev/null
+from migen.fhdl.structure import *
+from migen.fhdl import verilog, autofragment
+from migen.bus import csr
+from migen.sim.generic import Simulator, PureSimulable, TopLevel
+from migen.sim.icarus import Runner
+from migen.bus.transactions import *
+
+from miscope import trigger, recorder
+from miscope.tools.truthtable import *
+from miscope.tools.vcd import *
+
+TRIGGER_ADDR = 0x0000
+RECORDER_ADDR = 0x0200
+
+rec_done = False
+dat_rdy = False
+
+dat_vcd = []
+
+def term_prog(off, dat):
+ for i in range(4):
+ yield TWrite(off+3-i, (dat>>(8*i))&0xFF)
+
+
+def sum_prog(off, addr, dat):
+ we = 2
+ yield TWrite(off+3, addr%0xFF)
+ yield TWrite(off+2, (addr>>8)%0xFF)
+ yield TWrite(off+1, we+dat)
+ yield TWrite(off+0, 0)
+ for i in range(4):
+ yield TWrite(off+i,0)
+
+def csr_transactions(trigger0, recorder0):
+
+ # Trigger Prog
+ ##############################
+
+ # Term Prog
+ term_trans = []
+ term_trans += [term_prog(trigger0.ports[0].reg_base, 0x00000000)]
+ term_trans += [term_prog(trigger0.ports[1].reg_base, 0x00000004)]
+ term_trans += [term_prog(trigger0.ports[2].reg_base, 0x00000008)]
+ term_trans += [term_prog(trigger0.ports[3].reg_base, 0x0000000C)]
+ for t in term_trans:
+ for r in t:
+ yield r
+
+ # Sum Prog
+ sum_tt = gen_truth_table("term0 | term1 | term2 | term3")
+ sum_trans = []
+ for i in range(len(sum_tt)):
+ sum_trans.append(sum_prog(trigger0.sum.reg_base, i, sum_tt[i]))
+ for t in sum_trans:
+ for r in t:
+ yield r
+
+ # Recorder Prog
+ ##############################
+ #Reset
+ yield TWrite(recorder0.address + 0, 1)
+ yield TWrite(recorder0.address + 0, 0)
+
+ #Size
+ yield TWrite(recorder0.address + 3, 0)
+ yield TWrite(recorder0.address + 4, 64)
+
+ #Offset
+ yield TWrite(recorder0.address + 5, 0)
+ yield TWrite(recorder0.address + 6, 16)
+
+ #Arm
+ yield TWrite(recorder0.address + 1, 1)
+
+ # Wait Record to be done
+ ##############################
+ global rec_done
+ while not rec_done:
+ yield None
+
+ # Read recorded data
+ ##############################
+ global dat_rdy
+ for t in range(64):
+ yield TWrite(recorder0.address + 7, 1)
+ dat_rdy = False
+ yield TWrite(recorder0.address + 7, 0)
+ yield TRead(recorder0.address + 8)
+ yield TRead(recorder0.address + 9)
+ yield TRead(recorder0.address + 10)
+ yield TRead(recorder0.address + 11)
+ dat_rdy = True
+
+ dat_rdy = False
+
+ for t in range(512):
+ yield None
+
+
+trig_sig_val = 0
+
+
+def main():
+
+ # Trigger
+ term0 = trigger.Term(32)
+ term1 = trigger.Term(32)
+ term2 = trigger.Term(32)
+ term3 = trigger.Term(32)
+ trigger0 = trigger.Trigger(TRIGGER_ADDR, 32, 64, [term0, term1, term2, term3])
+
+ # Recorder
+ recorder0 = recorder.Recorder(RECORDER_ADDR, 32, 1024)
+
+ # Csr Master
+ csr_master0 = csr.Initiator(csr_transactions(trigger0, recorder0))
+
+ # Csr Interconnect
+ csrcon0 = csr.Interconnect(csr_master0.bus,
+ [
+ trigger0.bank.interface,
+ recorder0.bank.interface
+ ])
+
+ trig_sig = Signal(32)
+ comb = []
+ comb +=[
+ trigger0.in_trig.eq(trig_sig)
+ ]
+
+ comb += [
+ recorder0.trig_dat.eq(trig_sig),
+ recorder0.trig_hit.eq(trigger0.hit)
+ ]
+ # Term Test
+ def term_stimuli(s):
+ global trig_sig_val
+ s.wr(trig_sig,trig_sig_val)
+ trig_sig_val += 1
+ trig_sig_val = trig_sig_val % 256
+
+ # Recorder Data
+ def recorder_data(s):
+ global rec_done
+ if s.rd(recorder0.sequencer.rec_done) == 1:
+ rec_done = True
+
+ global dat_rdy
+ if dat_rdy:
+ print("%08X" %s.rd(recorder0._get_dat.field.w))
+ global dat_vcd
+ dat_vcd.append(s.rd(recorder0._get_dat.field.w))
+
+
+ # Simulation
+ def end_simulation(s):
+ s.interrupt = csr_master0.done
+ myvcd = Vcd()
+ myvcd.add(Var("wire", 32, "trig_dat", dat_vcd))
+ f = open("tb_Miscope_Out.vcd", "w")
+ f.write(str(myvcd))
+ f.close()
+
+
+ fragment = autofragment.from_local()
+ fragment += Fragment(comb=comb)
+ fragment += Fragment(sim=[term_stimuli])
+ fragment += Fragment(sim=[recorder_data])
+ fragment += Fragment(sim=[end_simulation])
+
+ sim = Simulator(fragment, Runner(),TopLevel("tb_MigScope.vcd"))
+ sim.run(2000)
+
+main()
+input()
+++ /dev/null
-from migen.fhdl.structure import *
-from migen.fhdl import verilog, autofragment
-from migen.bus import csr
-from migen.sim.generic import Simulator, PureSimulable, TopLevel
-from migen.sim.icarus import Runner
-from migen.bus.transactions import *
-from migen.bank import description, csrgen
-from migen.bank.description import *
-
-import sys
-sys.path.append("../")
-import spi2Csr
-
-def get_bit(dat, bit):
- return int(dat & (1<<bit) != 0)
-
-def set_bit(dat, bit):
- return dat | (1<<bit)
-
-def spi_transactions():
- yield TWrite(0x0000, 0x5A)
- yield TWrite(0x0001, 0xA5)
- yield TWrite(0x0002, 0x5A)
- yield TWrite(0x0003, 0xA5)
-
- for i in range(10):
- yield None
-
- yield TRead(0x0000)
- yield TRead(0x0001)
- yield TRead(0x0002)
- yield TRead(0x0003)
-
- for i in range(100):
- yield None
-
-class SpiMaster(PureSimulable):
- def __init__(self, spi, clk_ratio, generator):
- self.spi = spi
- self.clk_ratio = clk_ratio
- self.generator = generator
- self.transaction_start = 0
- self.transaction = None
- self.done = False
- self.r_dat = 0
-
- def do_simulation(self, s):
- a_w = self.spi.a_width
- d_w = self.spi.d_width
-
- if not self.done:
- if self.transaction is None:
- try:
- self.transaction = next(self.generator)
- except StopIteration:
- self.done = True
- self.transaction = None
- if self.transaction is not None:
- self.transaction_cnt = 0
- self.r_dat = 0
- print(self.transaction)
- elif isinstance(self.transaction, TWrite):
-
- # Clk
- if (int(self.transaction_cnt/(self.clk_ratio/2)))%2:
- s.wr(self.spi.spi_clk, 1)
- else:
- s.wr(self.spi.spi_clk, 0)
-
- # Mosi Addr
- if self.transaction_cnt < a_w*self.clk_ratio:
- bit = a_w-1-int((self.transaction_cnt)/self.clk_ratio)
- if int(self.transaction_cnt/self.clk_ratio) == 0:
- data = 1
- else:
- data = get_bit(self.transaction.address, bit)
- s.wr(self.spi.spi_mosi, data)
- # Mosi Data
- elif self.transaction_cnt >= a_w*self.clk_ratio and self.transaction_cnt < (a_w + d_w)*self.clk_ratio:
- bit = d_w-1-int((self.transaction_cnt-a_w*self.clk_ratio)/self.clk_ratio)
- data = get_bit(self.transaction.data,bit)
- s.wr(self.spi.spi_mosi, data)
- else:
- s.wr(self.spi.spi_mosi, 0)
-
- # Cs_n
- if self.transaction_cnt < (a_w + d_w)*self.clk_ratio:
- s.wr(self.spi.spi_cs_n,0)
- else:
- s.wr(self.spi.spi_cs_n, 1)
- s.wr(self.spi.spi_clk, 0)
- s.wr(self.spi.spi_mosi, 0)
- self.transaction = None
-
- # Incr transaction_cnt
- self.transaction_cnt +=1
-
- elif isinstance(self.transaction, TRead):
-
- # Clk
- if (int(self.transaction_cnt/(self.clk_ratio/2)))%2:
- s.wr(self.spi.spi_clk, 1)
- else:
- s.wr(self.spi.spi_clk, 0)
-
- # Mosi Addr
- if self.transaction_cnt < a_w*self.clk_ratio:
- bit = a_w-1-int((self.transaction_cnt)/self.clk_ratio)
- if int(self.transaction_cnt/self.clk_ratio) == 0:
- data = 0
- else:
- data = get_bit(self.transaction.address, bit)
- s.wr(self.spi.spi_mosi, data)
- else:
- s.wr(self.spi.spi_mosi, 0)
-
- # Miso Data
- if self.transaction_cnt >= a_w*self.clk_ratio and self.transaction_cnt%self.clk_ratio==self.clk_ratio/2:
- bit = d_w-1-int((self.transaction_cnt-a_w*self.clk_ratio)/self.clk_ratio)
- if s.rd(self.spi.spi_miso):
- self.r_dat = set_bit(self.r_dat, bit)
-
- # Cs_n
- if self.transaction_cnt < (a_w + d_w)*self.clk_ratio:
- s.wr(self.spi.spi_cs_n,0)
- else:
- s.wr(self.spi.spi_cs_n, 1)
- s.wr(self.spi.spi_clk, 0)
- s.wr(self.spi.spi_mosi, 0)
- self.transaction = None
- print("%02X" %self.r_dat)
-
- # Incr transaction_cnt
- self.transaction_cnt +=1
-
-
-def main():
- # Csr Slave
- scratch_reg0 = RegisterField("scratch_reg0", 32, reset=0, access_dev=READ_ONLY)
- scratch_reg1 = RegisterField("scratch_reg1", 32, reset=0, access_dev=READ_ONLY)
- scratch_reg2 = RegisterField("scratch_reg3", 32, reset=0, access_dev=READ_ONLY)
- scratch_reg3 = RegisterField("scratch_reg4", 32, reset=0, access_dev=READ_ONLY)
- regs = [scratch_reg0, scratch_reg1, scratch_reg2, scratch_reg3]
- bank0 = csrgen.Bank(regs,address=0x0000)
-
- # Spi2Csr
- spi2csr0 = spi2Csr.Spi2Csr(16,8)
-
-
- # Csr Interconnect
- csrcon0 = csr.Interconnect(spi2csr0.csr,
- [
- bank0.interface
- ])
-
- # Spi Master
- spi_master0 = SpiMaster(spi2csr0, 8, spi_transactions())
-
- # Simulation
- def end_simulation(s):
- s.interrupt = spi_master0.done
-
-
- fragment = autofragment.from_local()
- fragment += Fragment(sim=[end_simulation])
- sim = Simulator(fragment, Runner(),TopLevel("tb_spi2Csr.vcd"))
- sim.run(10000)
-
-main()
-input()
--- /dev/null
+from migen.fhdl.structure import *
+from migen.fhdl import verilog, autofragment
+from migen.bus import csr
+from migen.sim.generic import Simulator, PureSimulable, TopLevel
+from migen.sim.icarus import Runner
+from migen.bus.transactions import *
+from migen.bank import description, csrgen
+from migen.bank.description import *
+
+import miscope.bridges.spi2csr
+
+def get_bit(dat, bit):
+ return int(dat & (1<<bit) != 0)
+
+def set_bit(dat, bit):
+ return dat | (1<<bit)
+
+def spi_transactions():
+ yield TWrite(0x0000, 0x5A)
+ yield TWrite(0x0001, 0xA5)
+ yield TWrite(0x0002, 0x5A)
+ yield TWrite(0x0003, 0xA5)
+
+ for i in range(10):
+ yield None
+
+ yield TRead(0x0000)
+ yield TRead(0x0001)
+ yield TRead(0x0002)
+ yield TRead(0x0003)
+
+ for i in range(100):
+ yield None
+
+class SpiMaster(PureSimulable):
+ def __init__(self, spi, clk_ratio, generator):
+ self.spi = spi
+ self.clk_ratio = clk_ratio
+ self.generator = generator
+ self.transaction_start = 0
+ self.transaction = None
+ self.done = False
+ self.r_dat = 0
+
+ def do_simulation(self, s):
+ a_w = self.spi.a_width
+ d_w = self.spi.d_width
+
+ if not self.done:
+ if self.transaction is None:
+ try:
+ self.transaction = next(self.generator)
+ except StopIteration:
+ self.done = True
+ self.transaction = None
+ if self.transaction is not None:
+ self.transaction_cnt = 0
+ self.r_dat = 0
+ print(self.transaction)
+ elif isinstance(self.transaction, TWrite):
+
+ # Clk
+ if (int(self.transaction_cnt/(self.clk_ratio/2)))%2:
+ s.wr(self.spi.spi_clk, 1)
+ else:
+ s.wr(self.spi.spi_clk, 0)
+
+ # Mosi Addr
+ if self.transaction_cnt < a_w*self.clk_ratio:
+ bit = a_w-1-int((self.transaction_cnt)/self.clk_ratio)
+ if int(self.transaction_cnt/self.clk_ratio) == 0:
+ data = 1
+ else:
+ data = get_bit(self.transaction.address, bit)
+ s.wr(self.spi.spi_mosi, data)
+ # Mosi Data
+ elif self.transaction_cnt >= a_w*self.clk_ratio and self.transaction_cnt < (a_w + d_w)*self.clk_ratio:
+ bit = d_w-1-int((self.transaction_cnt-a_w*self.clk_ratio)/self.clk_ratio)
+ data = get_bit(self.transaction.data,bit)
+ s.wr(self.spi.spi_mosi, data)
+ else:
+ s.wr(self.spi.spi_mosi, 0)
+
+ # Cs_n
+ if self.transaction_cnt < (a_w + d_w)*self.clk_ratio:
+ s.wr(self.spi.spi_cs_n,0)
+ else:
+ s.wr(self.spi.spi_cs_n, 1)
+ s.wr(self.spi.spi_clk, 0)
+ s.wr(self.spi.spi_mosi, 0)
+ self.transaction = None
+
+ # Incr transaction_cnt
+ self.transaction_cnt +=1
+
+ elif isinstance(self.transaction, TRead):
+
+ # Clk
+ if (int(self.transaction_cnt/(self.clk_ratio/2)))%2:
+ s.wr(self.spi.spi_clk, 1)
+ else:
+ s.wr(self.spi.spi_clk, 0)
+
+ # Mosi Addr
+ if self.transaction_cnt < a_w*self.clk_ratio:
+ bit = a_w-1-int((self.transaction_cnt)/self.clk_ratio)
+ if int(self.transaction_cnt/self.clk_ratio) == 0:
+ data = 0
+ else:
+ data = get_bit(self.transaction.address, bit)
+ s.wr(self.spi.spi_mosi, data)
+ else:
+ s.wr(self.spi.spi_mosi, 0)
+
+ # Miso Data
+ if self.transaction_cnt >= a_w*self.clk_ratio and self.transaction_cnt%self.clk_ratio==self.clk_ratio/2:
+ bit = d_w-1-int((self.transaction_cnt-a_w*self.clk_ratio)/self.clk_ratio)
+ if s.rd(self.spi.spi_miso):
+ self.r_dat = set_bit(self.r_dat, bit)
+
+ # Cs_n
+ if self.transaction_cnt < (a_w + d_w)*self.clk_ratio:
+ s.wr(self.spi.spi_cs_n,0)
+ else:
+ s.wr(self.spi.spi_cs_n, 1)
+ s.wr(self.spi.spi_clk, 0)
+ s.wr(self.spi.spi_mosi, 0)
+ self.transaction = None
+ print("%02X" %self.r_dat)
+
+ # Incr transaction_cnt
+ self.transaction_cnt +=1
+
+
+def main():
+ # Csr Slave
+ scratch_reg0 = RegisterField("scratch_reg0", 32, reset=0, access_dev=READ_ONLY)
+ scratch_reg1 = RegisterField("scratch_reg1", 32, reset=0, access_dev=READ_ONLY)
+ scratch_reg2 = RegisterField("scratch_reg3", 32, reset=0, access_dev=READ_ONLY)
+ scratch_reg3 = RegisterField("scratch_reg4", 32, reset=0, access_dev=READ_ONLY)
+ regs = [scratch_reg0, scratch_reg1, scratch_reg2, scratch_reg3]
+ bank0 = csrgen.Bank(regs,address=0x0000)
+
+ # Spi2Csr
+ spi2csr0 = spi2csr.Spi2Csr(16,8)
+
+
+ # Csr Interconnect
+ csrcon0 = csr.Interconnect(spi2csr0.csr,
+ [
+ bank0.interface
+ ])
+
+ # Spi Master
+ spi_master0 = SpiMaster(spi2csr0, 8, spi_transactions())
+
+ # Simulation
+ def end_simulation(s):
+ s.interrupt = spi_master0.done
+
+
+ fragment = autofragment.from_local()
+ fragment += Fragment(sim=[end_simulation])
+ sim = Simulator(fragment, Runner(),TopLevel("tb_spi2Csr.vcd"))
+ sim.run(10000)
+
+main()
+input()
projects / litex.git / commitdiff