uint32_t offset, uint32_t value,
uint32_t range_id, uint32_t block_id);
-void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
- uint32_t offset, uint32_t value,
- struct r600_resource *bo,
- enum radeon_bo_usage usage);
-
#define r600_pipe_state_add_reg_bo(state, offset, value, bo, usage) _r600_pipe_state_add_reg_bo(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
#define r600_pipe_state_add_reg(state, offset, value) _r600_pipe_state_add_reg(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset))
range_id, block_id, NULL, 0);
}
-void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
- uint32_t offset, uint32_t value,
- struct r600_resource *bo,
- enum radeon_bo_usage usage)
-{
- if (bo) assert(usage);
-
- state->regs[state->nregs].id = offset;
- state->regs[state->nregs].block = NULL;
- state->regs[state->nregs].value = value;
- state->regs[state->nregs].bo = bo;
- state->regs[state->nregs].bo_usage = usage;
-
- state->nregs++;
- assert(state->nregs < R600_BLOCK_MAX_REG);
-}
-
uint32_t r600_translate_stencil_op(int s_op)
{
switch (s_op) {