Fix sel test

diff --git a/gram/test/test_frontend_wishbone.py b/gram/test/test_frontend_wishbone.py
index 02a9290c17693c90b02246fa9340946ce8952167..865e74a174b21d425ad8d4bbbca6d1bea021ea1b 100644 (file)
--- a/gram/test/test_frontend_wishbone.py
+++ b/gram/test/test_frontend_wishbone.py
@@ -236,9 +236,9 @@ class GramWishboneTestCase(FHDLTestCase):
 
             self.assertEqual((yield native_port.wdata.we), 1)
 
-            yield bus.stb.eq(0)
-            yield bus.cyc.eq(0)
-            yield native_port.wdata.ready.eq(0)
+            yield dut.bus.stb.eq(0)
+            yield dut.bus.cyc.eq(0)
+            yield dut.native_port.wdata.ready.eq(0)
             yield
 
         runSimulation(dut, process, "test_frontend_wishbone.vcd")