alter STATE CSR to support subvl

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 09467bc3b164887c33e017563a90ded7352f2437..c6d604a67d3cc703992adf39f08589b222d3debb 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -890,7 +890,8 @@ reg_t processor_t::get_csr(int which)
     case CSR_USVSTATE:
       return (state.sv().vl-1)            | ((state.sv().mvl-1)<<6) |
              (state.sv().srcoffs<<12)     | (state.sv().destoffs<<18) |
-             (state.sv().state_bank<<24)  | (state.sv().state_size<<26);
+             ((state.sv().subvl-1)<<24)   |
+             (state.sv().ssvoffs<<26)     | (state.sv().dsvoffs<<28);
     case CSR_USVMVL:
       return state.sv().mvl;
     case CSR_SVREGTOP: