x86: fix movsd bug on %xmm register

The movsd instruction should zero out half the register, but
does not do it. This changeset adds the necessary microop to
the instruction to cause correct behavior.

Change-Id: I5278da3634c78a97ed0586f687a36c6dc5a34c60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19068
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
index 81dfc7fee7ef67738b17e83207b9a3c299a65918..13e900d25ffd89d34a9116e20ab43fa41100c2fc 100644 (file)
--- a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
@@ -256,13 +256,13 @@ def macroop MOVSS_P_XMM {
 };
 
 def macroop MOVSD_XMM_M {
-    # Zero xmmh
+    lfpimm xmmh, 0
     ldfp xmml, seg, sib, disp, dataSize=8
 };
 
 def macroop MOVSD_XMM_P {
     rdip t7
-    # Zero xmmh
+    lfpimm xmmh, 0
     ldfp xmml, seg, riprel, disp, dataSize=8
 };