int ir3_ra(struct ir3_shader_variant *v, struct ir3_instruction **precolor, unsigned nprecolor);
/* legalize: */
-void ir3_legalize(struct ir3 *ir, bool *has_ssbo, bool *need_pixlod, int *max_bary);
+void ir3_legalize(struct ir3 *ir, struct ir3_shader_variant *so, int *max_bary);
/* ************************************************************************* */
/* instruction helpers */
/* We need to do legalize after (for frag shader's) the "bary.f"
* offsets (inloc) have been assigned.
*/
- ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
+ ir3_legalize(ir, so, &max_bary);
ir3_debug_print(ir, "AFTER LEGALIZE");
struct ir3_legalize_ctx {
struct ir3_compiler *compiler;
+ struct ir3_shader_variant *so;
gl_shader_stage type;
- bool has_ssbo;
- bool need_pixlod;
int max_bary;
};
if (is_tex(n) || (n->opc == OPC_META_TEX_PREFETCH)) {
regmask_set(&state->needs_sy, n->regs[0]);
- ctx->need_pixlod = true;
+ ctx->so->need_pixlod = true;
if (n->opc == OPC_META_TEX_PREFETCH)
has_tex_prefetch = true;
} else if (n->opc == OPC_RESINFO) {
}
if (is_ssbo(n->opc) || (is_atomic(n->opc) && (n->flags & IR3_INSTR_G)))
- ctx->has_ssbo = true;
+ ctx->so->has_ssbo = true;
/* both tex/sfu appear to not always immediately consume
* their src register(s):
}
void
-ir3_legalize(struct ir3 *ir, bool *has_ssbo, bool *need_pixlod, int *max_bary)
+ir3_legalize(struct ir3 *ir, struct ir3_shader_variant *so, int *max_bary)
{
struct ir3_legalize_ctx *ctx = rzalloc(ir, struct ir3_legalize_ctx);
bool progress;
+ ctx->so = so;
ctx->max_bary = -1;
ctx->compiler = ir->compiler;
ctx->type = ir->type;
}
} while (progress);
- *has_ssbo = ctx->has_ssbo;
- *need_pixlod = ctx->need_pixlod;
*max_bary = ctx->max_bary;
do {