power: Add support for real-mode addressing (translation is off)

This patch adds support for executing programs which don't have the
translation support (MSR[IR, DR] = 0). With this change, we should be
able to run 64 little endian elf binaries executing previleged
instructions with translation off.

Change-Id: Iaa64a37676874cee1ed1a0591b51b5e842774b45
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by:  Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>

diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
index faf6dfb9177e73722386d035568b1d3a1d17d57f..a73f673b175c00f9f8072e143aa1c3e2f3a28866 100644 (file)
--- a/src/arch/power/isa.cc
+++ b/src/arch/power/isa.cc
@@ -39,6 +39,8 @@
 
 #include "arch/power/isa.hh"
 
+#include "arch/power/miscregs.hh"
+#include "cpu/base.hh"
 #include "params/PowerISA.hh"
 
 namespace PowerISA
@@ -56,6 +58,20 @@ ISA::params() const
     return dynamic_cast<const Params *>(_params);
 }
 
+MiscReg
+ISA::readMiscRegNoEffect(int misc_reg) const
+{
+    assert(isValidMiscReg(misc_reg));
+    return regVal[misc_reg];
+}
+
+void
+ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+{
+    assert(isValidMiscReg(misc_reg));
+    regVal[misc_reg] = val;
+}
+
 }
 
 PowerISA::ISA *

diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 9769f8fd1af7e10d01e89678c024fc9d92ba5335..d123e2ffe18cfbb71c145ef6c5eb716525fca9e7 100644 (file)
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -33,6 +33,7 @@
 #ifndef __ARCH_POWER_ISA_HH__
 #define __ARCH_POWER_ISA_HH__
 
+#include "arch/power/miscregs.hh"
 #include "arch/power/registers.hh"
 #include "arch/power/types.hh"
 #include "base/logging.hh"
@@ -50,23 +51,18 @@ namespace PowerISA
 class ISA : public SimObject
 {
   protected:
+    MiscReg regVal[NumMiscRegs];
     MiscReg dummy;
-    MiscReg miscRegs[NumMiscRegs];
 
   public:
     typedef PowerISAParams Params;
-
     void
     clear()
     {
+        memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
     }
 
-    MiscReg
-    readMiscRegNoEffect(int misc_reg) const
-    {
-        fatal("Power does not currently have any misc regs defined\n");
-        return dummy;
-    }
+    MiscReg readMiscRegNoEffect(int misc_reg) const;
 
     MiscReg
     readMiscReg(int misc_reg, ThreadContext *tc)
@@ -75,11 +71,7 @@ class ISA : public SimObject
         return dummy;
     }
 
-    void
-    setMiscRegNoEffect(int misc_reg, const MiscReg &val)
-    {
-        fatal("Power does not currently have any misc regs defined\n");
-    }
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 
     void
     setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)

diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index ff2f94fb6d6bcf948fdf09817a74492b83a2dec4..88abd9407877adc7fadacab0cede48c0594464fa 100644 (file)
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -41,7 +41,9 @@
 #include <vector>
 
 #include "arch/power/faults.hh"
+#include "arch/power/miscregs.hh"
 #include "arch/power/pagetable.hh"
+#include "arch/power/registers.hh"
 #include "arch/power/utility.hh"
 #include "base/inifile.hh"
 #include "base/str.hh"
@@ -312,13 +314,39 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 Fault
 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 {
-    if (FullSystem)
-        fatal("translate atomic not yet implemented in full system mode.\n");
-
+    if (FullSystem){
+       Msr msr = tc->readIntReg(MISCREG_MSR);
+        if (mode == Execute){
+            if (msr.ir)
+                fatal("Translate Atomic not Implemented for POWER");
+            else{
+                Addr vaddr = req->getVaddr();
+                DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
+                Addr paddr = vaddr;
+                DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
+                req->setPaddr(paddr);
+                return NoFault;
+            }
+        }
+        else{
+            if (msr.dr)
+                fatal("Translate Atomic not Implemented for POWER");
+            else{
+                Addr vaddr = req->getVaddr();
+                DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
+                Addr paddr = vaddr;
+                DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
+                req->setPaddr(paddr);
+                return NoFault;
+            }
+        }
+    }
     if (mode == Execute)
-        return translateInst(req, tc);
-    else
+         return translateInst(req, tc);
+    else{
+        std::cout<<"translateData"<<std::endl;
         return translateData(req, tc, mode == Write);
+   }
 }
 
 void