using namespace TheISA;
BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
- : BaseCPU(params), cpu_id(0)
+ : BaseCPU(params), cpuId(0)
{
}
void regStats();
/** Sets this CPU's ID. */
- void setCpuId(int id) { cpu_id = id; }
+ void setCpuId(int id) { cpuId = id; }
/** Reads this CPU's ID. */
- int readCpuId() { return cpu_id; }
+ int readCpuId() { return cpuId; }
protected:
- int cpu_id;
+ int cpuId;
};
/**
BlkType *tempBlock;
/**
- * Can this cache should allocate a block on a line-sized write miss.
+ * This cache should allocate a block on a line-sized write miss.
*/
const bool doFastWrites;
* @param lat The latency of the access.
* @param writebacks List for any writebacks that need to be performed.
* @param update True if the replacement data should be updated.
- * @return Pointer to the cache block touched by the request. NULL if it
- * was a miss.
+ * @return Boolean indicating whether the request was satisfied.
*/
bool access(PacketPtr pkt, BlkType *&blk,
int &lat, PacketList &writebacks);