i965: Set Line Width correctly on Cherryview and Skylake.

Line Width moved to DW1 bits 29:12.  It's actually now a U11.7.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index ee3d87196f6b0180b25f21e93d30b139e8e656bd..53cd75effad34f737ae2c46ca62f077af4f7cd24 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1805,6 +1805,7 @@ enum brw_message_target {
 # define GEN6_SF_SWIZZLE_ENABLE                                (1 << 21)
 # define GEN6_SF_POINT_SPRITE_UPPERLEFT                        (0 << 20)
 # define GEN6_SF_POINT_SPRITE_LOWERLEFT                        (1 << 20)
+# define GEN9_SF_LINE_WIDTH_SHIFT                      12 /* U11.7 */
 # define GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT           11
 # define GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT           4
 /* DW2 */

diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index 1d7b93261ac890f2caa2515495af856d6499fe53..6aa7b4d50f3841bf28f7ea8e31b09cfc426330f6 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -152,7 +152,11 @@ upload_sf(struct brw_context *brw)
    uint32_t line_width_u3_7 = U_FIXED(CLAMP(ctx->Line.Width, 0.0, 7.99), 7);
    if (line_width_u3_7 == 0)
       line_width_u3_7 = 1;
-   dw2 |= line_width_u3_7 << GEN6_SF_LINE_WIDTH_SHIFT;
+   if (brw->gen >= 9 || brw->is_cherryview) {
+      dw1 |= line_width_u3_7 << GEN9_SF_LINE_WIDTH_SHIFT;
+   } else {
+      dw2 |= line_width_u3_7 << GEN6_SF_LINE_WIDTH_SHIFT;
+   }
 
    if (ctx->Line.SmoothFlag) {
       dw2 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;