8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
#endif
- unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
+ unsigned vgpr;
+ if (ctx->type == PIPE_SHADER_VERTEX)
+ vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
+ else
+ vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
+
for (unsigned i = 0; i < 5; i++) {
unsigned param = ctx->param_gs_vtx01_offset + i;
ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
if (ctx->type == PIPE_SHADER_VERTEX) {
declare_vs_specific_input_sgprs(ctx, &fninfo);
} else {
- /* TESS_EVAL (and also GEOMETRY):
- * Declare as many input SGPRs as the VS has. */
ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
- add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
- ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
+ if (!HAVE_32BIT_POINTERS) {
+ /* Declare as many input SGPRs as the VS has. */
+ add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
+ ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
+ }
}
if (!HAVE_32BIT_POINTERS) {
if (ctx->type == PIPE_SHADER_VERTEX ||
ctx->type == PIPE_SHADER_TESS_EVAL) {
+ unsigned num_user_sgprs;
+
+ if (ctx->type == PIPE_SHADER_VERTEX)
+ num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
+ else
+ num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
+
/* ES return values are inputs to GS. */
- for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
+ for (i = 0; i < 8 + num_user_sgprs; i++)
returns[num_returns++] = ctx->i32; /* SGPRs */
for (i = 0; i < 5; i++)
returns[num_returns++] = ctx->f32; /* VGPRs */
si_init_function_info(&fninfo);
if (ctx->screen->info.chip_class >= GFX9) {
- num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
+ if (key->gs_prolog.states.gfx9_prev_is_vs)
+ num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
+ else
+ num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
num_vgprs = 5; /* ES inputs are not needed by GS */
} else {
num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
/* GS limits */
GFX6_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
- GFX9_GS_NUM_USER_SGPR = GFX9_MERGED_NUM_USER_SGPR,
+#if HAVE_32BIT_POINTERS
+ GFX9_VSGS_NUM_USER_SGPR = SI_VS_NUM_USER_SGPR,
+ GFX9_TESGS_NUM_USER_SGPR = SI_TES_NUM_USER_SGPR,
+#else
+ GFX9_VSGS_NUM_USER_SGPR = GFX9_MERGED_NUM_USER_SGPR,
+ GFX9_TESGS_NUM_USER_SGPR = GFX9_MERGED_NUM_USER_SGPR,
+#endif
SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS + (HAVE_32BIT_POINTERS ? 1 : 2),
/* PS only */
struct si_gs_prolog_bits {
unsigned tri_strip_adj_fix:1;
+ unsigned gfx9_prev_is_vs:1;
};
/* Common PS bits between the shader key and the prolog key. */
unsigned num_user_sgprs;
if (es_type == PIPE_SHADER_VERTEX)
- num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_GS_NUM_USER_SGPR);
+ num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
else
- num_user_sgprs = GFX9_GS_NUM_USER_SGPR;
+ num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
key, &key->part.gs.vs_prolog);
key->part.gs.es = sctx->vs_shader.cso;
+ key->part.gs.prolog.gfx9_prev_is_vs = 1;
}
/* Merged ES-GS can have unbalanced wave usage.