uint64_t old_va = rbuffer->gpu_address;
unsigned num_elems = sctx->vertex_elements ?
sctx->vertex_elements->count : 0;
+ struct si_pipe_sampler_view *view;
/* Reallocate the buffer in the same pipe_resource. */
r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
}
}
- /* Texture buffers. */
+ /* Texture buffers - update virtual addresses in sampler view descriptors. */
+ LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
+ if (view->base.texture == buf) {
+ si_desc_reset_buffer_offset(ctx, view->state, old_va, buf);
+ }
+ }
+ /* Texture buffers - update bindings. */
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
struct si_sampler_views *views = &sctx->samplers[shader].views;
bool found = false;
while (mask) {
unsigned i = u_bit_scan(&mask);
if (views->views[i]->texture == buf) {
- /* This updates the sampler view directly. */
- si_desc_reset_buffer_offset(ctx, views->desc_data[i],
- old_va, buf);
-
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
rbuffer, RADEON_USAGE_READ,
RADEON_PRIO_SHADER_BUFFER_RO);
struct pipe_resource *texture,
const struct pipe_sampler_view *state)
{
+ struct si_context *sctx = (struct si_context*)ctx;
struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
struct r600_texture *tmp = (struct r600_texture*)texture;
const struct util_format_description *desc;
S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
S_008F0C_NUM_FORMAT(num_format) |
S_008F0C_DATA_FORMAT(format);
+
+ LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
return &view->base;
}
static void si_sampler_view_destroy(struct pipe_context *ctx,
struct pipe_sampler_view *state)
{
- struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
+ struct si_pipe_sampler_view *view = (struct si_pipe_sampler_view *)state;
+
+ if (view->resource->b.b.target == PIPE_BUFFER)
+ LIST_DELINIT(&view->list);
pipe_resource_reference(&state->texture, NULL);
- FREE(resource);
+ FREE(view);
}
static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)