ISAs: Streamline some spots where Mem is used in the ISA descriptions.

diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa
index ebf0bfa214a0c930600b1d35a2fd09844bad9d93..0361ee998be2ebbdd3b9f3f0fcf69485cc19879b 100644 (file)
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -125,15 +125,13 @@ def template LoadCompleteAcc {{
     {
         Addr EA;
         Fault fault = NoFault;
-        %(mem_acc_type)s val;
 
         %(op_decl)s;
         %(op_rd)s;
 
         EA = xc->getEA();
 
-        getMem(pkt, val, traceData);
-        *((%(mem_acc_type)s*)&Mem) = val;
+        getMem(pkt, Mem, traceData);
 
         if (fault == NoFault) {
             %(memacc_code)s;

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index d15d1eb2b32011463b3eaac7bb0b053cc1b67972..82c712eb02dd9e0a361af07f9aacd8be7fdda60c 100644 (file)
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1125,10 +1125,10 @@ decode OP default Unknown::unknown()
                   }});
         }
         format Load {
-            0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
-            0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
-            0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
-            0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
+            0x08: ldsw({{Rd = Mem.sw;}});
+            0x09: ldsb({{Rd = Mem.sb;}});
+            0x0A: ldsh({{Rd = Mem.shw;}});
+            0x0B: ldx({{Rd = Mem.sdw;}});
         }
         0x0D: Swap::ldstub({{Mem.ub = 0xFF;}},
                            {{
@@ -1223,10 +1223,10 @@ decode OP default Unknown::unknown()
                   }});
         }
         format LoadAlt {
-            0x18: ldswa({{Rd = (int32_t)Mem.sw;}});
-            0x19: ldsba({{Rd = (int8_t)Mem.sb;}});
-            0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
-            0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
+            0x18: ldswa({{Rd = Mem.sw;}});
+            0x19: ldsba({{Rd = Mem.sb;}});
+            0x1A: ldsha({{Rd = Mem.shw;}});
+            0x1B: ldxa({{Rd = Mem.sdw;}});
         }
         0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}},
                            {{