Juggle opt calls in synth_xilinx

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 93d60f60bb885616ed16c2789364d2c990be0b8a..2536780289877a22b9e9594c3b9d2287d2f38ecb 100644 (file)
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -31,7 +31,6 @@ module \$shiftx (A, B, Y);
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
-  localparam NUM = A_WIDTH/Y_WIDTH;
   generate
     genvar i, j;
     if (B_SIGNED) begin
@@ -41,51 +40,57 @@ module \$shiftx (A, B, Y);
       else
         wire _TECHMAP_FAIL_ = 1;
     end
-    else if (NUM <= 4) begin
+    else if (Y_WIDTH > 1) begin
+      for (i = 0; i < Y_WIDTH; i++) begin
+        wire [A_WIDTH/Y_WIDTH-1:0] A_i;
+        for (j = 0; j < A_WIDTH/Y_WIDTH; j++)
+          assign A_i[j] = A[i*Y_WIDTH+j];
+        wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_i = B/Y_WIDTH;
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_i), .Y(Y[i]));
+      end
+    end
+    else if (B_WIDTH < 3) begin
       wire _TECHMAP_FAIL_ = 1;
     end
-    else if (NUM <= 8) begin
-      localparam a_width0 = Y_WIDTH * 4;
+    else if (B_WIDTH == 3) begin
+      localparam a_width0 = 2 ** 2;
       localparam a_widthN = A_WIDTH - a_width0;
-      wire [Y_WIDTH-1:0] T0, T1;
+      wire T0, T1;
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[B_WIDTH-2:0]), .Y(T0));
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
-      for (i = 0; i < Y_WIDTH; i++)
-        MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i]));
+      MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i]));
     end
-    else if (NUM <= 16) begin
-      localparam a_width0 = Y_WIDTH * 4;
+    else if (B_WIDTH == 4) begin
+      localparam a_width0 = 2 ** 3;
       localparam num_mux8 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux8*a_width0;
-      wire [Y_WIDTH*4-1:0] T;
-      wire [Y_WIDTH-1:0] T0, T1;
-      for (i = 0; i < 4; i++)
+      wire [B_WIDTH-1:0] T;
+      wire T0, T1;
+      for (i = 0; i < B_WIDTH; i++)
         if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]),          .Y(T[i]));
         else if (i == num_mux8 && a_widthN > 0)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         else
-          assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};
-      for (i = 0; i < Y_WIDTH; i++) begin
-        MUXF7 fpga_mux_0 (.I0(T[0*Y_WIDTH+i]), .I1(T[1*Y_WIDTH+i]), .S(B[B_WIDTH-2]), .O(T0[i]));
-        MUXF7 fpga_mux_1 (.I0(T[2*Y_WIDTH+i]), .I1(T[3*Y_WIDTH+i]), .S(B[B_WIDTH-2]), .O(T1[i]));
-        MUXF8 fpga_mux_2 (.I0(T0[i]),          .I1(T1[i]),          .S(B[B_WIDTH-1]), .O(Y[i]));
-      end
+          assign T[i] = 1'bx;
+      MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[B_WIDTH-2]), .O(T0));
+      MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[B_WIDTH-2]), .O(T1));
+      MUXF8 fpga_mux_2 (.I0(T0),   .I1(T1),   .S(B[B_WIDTH-1]), .O(Y));
     end
     else begin
-      localparam a_width0 = Y_WIDTH * 16;
+      localparam a_width0 = 2 ** 4;
       localparam num_mux16 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux16*a_width0;
-      wire [Y_WIDTH * (2 ** ($clog2(NUM)-4))-1:0] T;
-      for (i = 0; i < 2 ** ($clog2(NUM)-4); i++)
+      wire [(2**(B_WIDTH-4))-1:0] T;
+      for (i = 0; i < 2 ** (B_WIDTH-4); i++)
         if (i < num_mux16)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH($clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[$clog2(a_width0)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]),                .Y(T[i]));
         else if (i == num_mux16 && a_widthN > 0) begin
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_width0)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         end
         else
-          assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(Y_WIDTH * (2 ** ($clog2(NUM)-4))), .B_WIDTH(B_WIDTH-$clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:$clog2(a_width0)]), .Y(Y));
+          assign T[i] = 1'bx;
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
     end
   endgenerate
 endmodule

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 10902a5606b7cad86ae25dc80d6e6f096f0b423f..0058f626fb49a92a0a1d92cea3332d4b4fe3ced9 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -118,7 +118,7 @@ struct SynthXilinxPass : public Pass
                log("\n");
                log("    map_cells:\n");
                log("        techmap -map +/xilinx/cells_map.v\n");
-               log("        clean\n");
+               log("        opt -fast\n");
                log("\n");
                log("    map_luts:\n");
                log("        techmap -map +/techmap.v\n");
@@ -258,11 +258,10 @@ struct SynthXilinxPass : public Pass
 
                if (check_label(active, run_from, run_to, "fine"))
                {
-                       Pass::call(design, "opt -fast -full");
+                       Pass::call(design, "opt -fast");
                        Pass::call(design, "memory_map");
                        Pass::call(design, "dffsr2dff");
                        Pass::call(design, "dff2dffe");
-                       Pass::call(design, "opt -full");
 
                        if (vpr) {
                                Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
@@ -282,6 +281,7 @@ struct SynthXilinxPass : public Pass
 
                if (check_label(active, run_from, run_to, "map_luts"))
                {
+                       Pass::call(design, "opt -full");
                        Pass::call(design, "techmap -map +/techmap.v");
                        if (abc == "abc9")
                                Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));