gas/testsuite/

	* gas/aarch64/msr.s: Add tests.
	* gas/aarch64/msr.d: Update.

include/opcode

	* aarch64.h (aarch64_pstatefields): Change element type to
	aarch64_sys_reg.

opcodes/

	* aarch64-opc.c (aarch64_pstatefields): Update.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 4d8e7dee3c330c2090a7cbd3eaed811b33bd615d..be531577a2620a1492e64fcd51bb2e11e2eaffe5 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+       * gas/aarch64/msr.s: Add tests.
+       * gas/aarch64/msr.d: Update.
+
 2013-11-19  Catherine Moore  <clm@codesourcery.com>
 
        * gas/mips/fix-pmc-rm7000-1.d: New.

diff --git a/gas/testsuite/gas/aarch64/msr.d b/gas/testsuite/gas/aarch64/msr.d
index c6c32200a4153a09c8934167b4a2ab70172b7a7b..750cae119abb85a748d02735ed920935859930e3 100644 (file)
--- a/gas/testsuite/gas/aarch64/msr.d
+++ b/gas/testsuite/gas/aarch64/msr.d
@@ -13,3 +13,5 @@ Disassembly of section \.text:
   14:  d5034fff        msr     daifclr, #0xf
   18:  d51b4220        msr     daif, x0
   1c:  d53b4220        mrs     x0, daif
+  20:  d50040bf        msr     spsel, #0x0
+  24:  d50041bf        msr     spsel, #0x1

diff --git a/gas/testsuite/gas/aarch64/msr.s b/gas/testsuite/gas/aarch64/msr.s
index 9f67d98771343abab10e785c03726a03114fba35..01018c289d1df399485e824aa07f8228184d182a 100644 (file)
--- a/gas/testsuite/gas/aarch64/msr.s
+++ b/gas/testsuite/gas/aarch64/msr.s
@@ -1,5 +1,5 @@
 /*
-   Copyright 2011, 2012 Free Software Foundation, Inc.
+   Copyright 2011-2013 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of GAS.
@@ -31,3 +31,6 @@ func:
 
        msr daif, x0
        mrs x0, daif
+
+       msr spsel, #0
+       msr spsel, #1

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index f4d1b0665ab90e94d2ceb569522e8de2b7de3203..216736daedeb4740e7bfcbd43ff6ab7a7aa8e6ca 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+       * aarch64.h (aarch64_pstatefields): Change element type to
+       aarch64_sys_reg.
+
 2013-11-18  Renlin Li  <Renlin.Li@arm.com>
 
        * arm.h (ARM_AEXT_V7VE): New define.

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 4a3a312b68338e3395970492453469ab50dad5e5..053294e33588fad8f4e8c1d3a3acdef226d03bba 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -611,7 +611,6 @@ struct aarch64_name_value_pair
 };
 
 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
-extern const struct aarch64_name_value_pair aarch64_pstatefields [];
 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 
@@ -623,6 +622,7 @@ typedef struct
 } aarch64_sys_reg;
 
 extern const aarch64_sys_reg aarch64_sys_regs [];
+extern const aarch64_sys_reg aarch64_pstatefields [];
 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 
 typedef struct

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8ed5de9c2b6b07da9d0d3fd77b6c609430b1d56a..8557c6d0cf943c230e00dd830f188e6e14df5442 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+       * aarch64-opc.c (aarch64_pstatefields): Update.
+
 2013-11-19  Catherine Moore  <clm@codesourcery.com>
 
        * micromips-opc.c (LM): Define.

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index af1472a58240659a2de0dcec331423740d2123da..43133279df6e21d2b62d74030dd4c5d358022a88 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3019,12 +3019,12 @@ aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
   return (reg->flags & F_DEPRECATED) != 0;
 }
 
-const struct aarch64_name_value_pair aarch64_pstatefields [] =
+const aarch64_sys_reg aarch64_pstatefields [] =
 {
-  { "spsel",            0x05  },
-  { "daifset",          0x1e  },
-  { "daifclr",          0x1f  },
-  { 0,          CPENC(0,0,0,0,0)  },
+  { "spsel",            0x05,  0 },
+  { "daifset",          0x1e,  0 },
+  { "daifclr",          0x1f,  0 },
+  { 0,          CPENC(0,0,0,0,0), 0 },
 };
 
 const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =