get the predicate inv argument as well

diff --git a/riscv/sv.cc b/riscv/sv.cc
index 25f9e545c7235cb487595174639dfe553946d673..946281ae4e92df7902502bd8f2b6333dd23cbbaa 100644 (file)
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -213,6 +213,11 @@ reg_spec_t sv_insn_t::remap(uint64_t reg, bool intreg, int *voffs)
  * registers (i.e. XLEN bits).
  */
 reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing)
+{
+    bool inv = false;
+    return predicate(reg, intreg, zeroing, inv);
+}
+reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing, bool &inv)
 {
   sv_reg_entry *pr = get_regentry(reg, intreg);
   if (!pr->active)

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 07274870d0e0137e1df2f8a9baeb10f4233cfc07..9a0b76eee3214f7c7ed33dbb8b8254719e81769c 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -97,6 +97,7 @@ public:
   sv_reg_entry* get_regentry(uint64_t reg, bool isint);
   sv_pred_entry* get_predentry(uint64_t reg, bool isint);
   reg_t predicate(uint64_t reg, bool isint, bool &zeroing);
+  reg_t predicate(uint64_t reg, bool isint, bool &zeroing, bool &inv);
 
   void reset_vloop_check(void) { vloop_continue = false; }
   bool stop_vloop(void);