test: change UART baudrate and test SATACONTRemover

diff --git a/targets/test.py b/targets/test.py
index 431fce2e2fa6a3ef97cb38eb715b83512896da65..9f92c81c5c6b7ac95a2ce837d96662557559b814 100644 (file)
--- a/targets/test.py
+++ b/targets/test.py
@@ -60,7 +60,7 @@ class UART2WB(Module):
        interrupt_map = {}
        cpu_type = None
        def __init__(self, platform, clk_freq):
-               self.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq)
+               self.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600)
 
                # CSR bridge   0x00000000 (shadow @0x00000000)
                self.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
@@ -159,7 +159,8 @@ class VeryBasicPHYStim(Module, AutoCSR):
                self.cont_remover = SATACONTRemover(phy_description(32))
                self.comb += [
                        self.cont_inserter.source.connect(phy.sink),
-                       phy.source.connect(self.cont_remover.sink)
+                       phy.source.connect(self.cont_remover.sink),
+                       self.cont_remover.source.ack.eq(1)
                ]
                self.sync += [
                        self.cont_inserter.sink.stb.eq(1),
@@ -201,20 +202,6 @@ class TestDesign(UART2WB, AutoCSR):
                        crg = self.sata_phy.crg
 
                        debug = (
-                               trx.rxresetdone,
-                               trx.txresetdone,
-
-                               trx.rxuserrdy,
-                               trx.txuserrdy,
-
-                               trx.rxelecidle,
-                               trx.rxcominitdet,
-                               trx.rxcomwakedet,
-
-                               trx.txcomfinish,
-                               trx.txcominit,
-                               trx.txcomwake,
-
                                ctrl.ready,
                                ctrl.sink.data,
                                ctrl.sink.charisk,
@@ -226,12 +213,16 @@ class TestDesign(UART2WB, AutoCSR):
                                self.sata_phy.sink.stb,
                                self.sata_phy.sink.data,
                                self.sata_phy.sink.charisk,
+
+                               self.stim.cont_remover.source.stb,
+                               self.stim.cont_remover.source.data,
+                               self.stim.cont_remover.source.charisk
                        )
 
                        self.comb += platform.request("user_led", 2).eq(crg.ready)
                        self.comb += platform.request("user_led", 3).eq(ctrl.ready)
 
-                       self.mila = MiLa(depth=512, dat=Cat(*debug))
+                       self.mila = MiLa(depth=2048, dat=Cat(*debug))
                        self.mila.add_port(Term)
 
                        if export_mila:

diff --git a/test/config.py b/test/config.py
index b9e77f56b82d66be555a219c837e6f6b1240b769..c27ac82141dc93d8f557a06875aea8b8c809564f 100644 (file)
--- a/test/config.py
+++ b/test/config.py
@@ -5,5 +5,5 @@ busword = 8
 debug_wb = False
 
 com = 2
-baud = 115200
+baud = 921600
 wb = Uart2Wishbone(com, baud, csr_csv_file, busword, debug_wb)
\ No newline at end of file

diff --git a/test/test_mila.py b/test/test_mila.py
index fbe95ccb7633f51a9290550efdf468b69b435154..584a94f6e575268550f94b938f2564b599ea392e 100644 (file)
--- a/test/test_mila.py
+++ b/test/test_mila.py
@@ -4,11 +4,8 @@ from miscope.host.drivers import MiLaDriver
 mila = MiLaDriver(wb.regs, "mila", use_rle=False)
 wb.open()
 ###
-trigger0 = mila.trx_rxelecidle0_o*0
-mask0 = mila.trx_rxelecidle0_m
-
-#trigger0 = mila.ctrl_align_detect_o
-#mask0 = mila.ctrl_align_detect_m
+trigger0 = mila.cont_remover_source_stb_o*1
+mask0 = mila.cont_remover_source_stb_m
 
 trigger0 = 0
 mask0 = 0
@@ -17,7 +14,7 @@ mila.prog_term(port=0, trigger=trigger0, mask=mask0)
 mila.prog_sum("term")
 
 # Trigger / wait / receive
-mila.trigger(offset=8, length=512)
+mila.trigger(offset=32, length=1024)
 mila.wait_done()
 mila.read()
 mila.export("dump.vcd")