Added final checks to "synth" and "synth_xilinx"

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index a50db53ee151f6642aaa6270e0dad18e4f5f5df3..56ab6eaff679d209f0d613df929b337a0c373a3e 100644 (file)
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -90,12 +90,14 @@ struct SynthPass : public Pass {
                log("        techmap\n");
                log("        opt -fast\n");
        #ifdef YOSYS_ENABLE_ABC
-               log("\n");
-               log("    abc:\n");
                log("        abc -fast\n");
                log("        opt -fast\n");
        #endif
                log("\n");
+               log("    check:\n");
+               log("        hierarchy -check\n");
+               log("        check\n");
+               log("\n");
        }
        virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
        {
@@ -172,15 +174,20 @@ struct SynthPass : public Pass {
                        Pass::call(design, "opt -full");
                        Pass::call(design, "techmap");
                        Pass::call(design, "opt -fast");
+
+                       if (!noabc) {
+               #ifdef YOSYS_ENABLE_ABC
+                               Pass::call(design, "abc -fast");
+                               Pass::call(design, "opt -fast");
+               #endif
+                       }
                }
 
-       #ifdef YOSYS_ENABLE_ABC
-               if (check_label(active, run_from, run_to, "abc") && !noabc)
+               if (check_label(active, run_from, run_to, "check"))
                {
-                       Pass::call(design, "abc -fast");
-                       Pass::call(design, "opt -fast");
+                       Pass::call(design, "hierarchy -check");
+                       Pass::call(design, "check");
                }
-       #endif
 
                log_pop();
        }

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7812fa29014cc9e54f6af028f4368f5c5e7db13c..02207593a2b9d0e571d58c22c4c5c4a21e91694f 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -98,6 +98,10 @@ struct SynthXilinxPass : public Pass {
                log("        techmap -map +/xilinx/cells_map.v\n");
                log("        clean\n");
                log("\n");
+               log("    check:\n");
+               log("        hierarchy -check\n");
+               log("        check -noinit\n");
+               log("\n");
                log("    edif:\n");
                log("        write_edif synth.edif\n");
                log("\n");
@@ -195,6 +199,12 @@ struct SynthXilinxPass : public Pass {
                        Pass::call(design, "clean");
                }
 
+               if (check_label(active, run_from, run_to, "check"))
+               {
+                       Pass::call(design, "hierarchy -check");
+                       Pass::call(design, "check -noinit");
+               }
+
                if (check_label(active, run_from, run_to, "edif"))
                {
                        if (!edif_file.empty())