add vector length pseudocode

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index a8bc2f170d2787b38374c9964c5772830c4687d0..ad2ced559b285622555951a06b1df497a92124b2 100644 (file)
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -422,11 +422,12 @@ Pseudo-code (excludes CSR SIMD bitwidth):
           vreg[rd+j][i] = mem[sreg[base] + offs + j*stride];
         }
 
-Taking CSR (SIMD) bitwidth into account involves extending vl according
-to the "Bitwidth Virtual Register Reordering" scheme shown in the Appendix.
+Taking CSR (SIMD) bitwidth into account involves using the vector
+length and register encoding according to the "Bitwidth Virtual Register
+Reordering" scheme shown in the Appendix (see function "regoffs").
 
 A similar instruction exists for STORE, with identical topological
-translation of all features.
+translation of all features.  **TODO**
 
 # Note on implementation of parallelism