include auto-generated identification of use of registers per op

modified id_regs.py to take a single argument (file in riscv/insns to parse)
added call to id_regs.py in riscv.mk.in
included the auto-generated file in the insn_template.cc

now each instruction has a way - BEFORE the emulated instruction is called -
to identify which registers (RD, RS1-3, FRD, FRS1-3) are going to be used.

diff --git a/id_regs.py b/id_regs.py
index 54443557e2f6e2c7022eca7f087e2874ec043b98..3f5290d41ca77b2871da5dbdbe7e60d3076032d3 100644 (file)
--- a/id_regs.py
+++ b/id_regs.py
@@ -19,9 +19,16 @@
 """
 
 import os
+import sys
 
 insns_dir = "./riscv/insns"
 def list_insns():
+    if len(sys.argv) == 2:
+        fullfname = sys.argv[1]
+        pth, fname = os.path.split(fullfname)
+        insn = fname[:-2]
+        return [(fullfname, insn)]
+
     res = []
     for fname in os.listdir(insns_dir):
         if not fname.endswith(".h"):

diff --git a/riscv/insn_template.cc b/riscv/insn_template.cc
index 9bfda57b48d62be046946e9d21321821db803ab5..61ec15f0097a3cc5e22e9c29010be97db802e6a5 100644 (file)
--- a/riscv/insn_template.cc
+++ b/riscv/insn_template.cc
@@ -22,6 +22,7 @@
 #define INCLUDEFILE "insns/NAME.h"
 #define INSNCODE OPCODE
 #include "sv_decode.h"
+#include "insns/regs_NAME.h"
 #define FN rv32_NAME
 #define ISASZ 32
 #include "insn_template_sv.cc"

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 80755e711c181794e3ea9cb96ea40443d06e1d2b..c52d5c0addf6aed2ab6ad57fe8258b800fbcc215 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -308,6 +308,7 @@ insn_list.h: $(src_dir)/riscv/riscv.mk.in
 
 $(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
        sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@
+       python id_regs.py $(src_dir)/riscv/insns/$(subst .cc,,$@).h
 
 riscv_junk = \
        $(riscv_gen_srcs) \