-Traceback (most recent call last):
- File "<string>", line 1, in <module>
- File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main
- exec filecode in scope
- File "tests/run.py", line 78, in <module>
- execfile(joinpath(tests_root, category, mode, name, 'test.py'))
- File "tests/quick/se/20.eio-short/test.py", line 29, in <module>
- root.system.cpu.workload = EioProcess(file = binpath('anagram',
-NameError: name 'EioProcess' is not defined
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+hack: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:36:31
-gem5 started May 8 2012 15:37:08
-gem5 executing on piton
+gem5 compiled Feb 29 2012 00:47:21
+gem5 started Feb 29 2012 00:51:57
+gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 250015500 because a thread reached the max instruction count
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000250 # Number of seconds simulated
+sim_ticks 250015500 # Number of ticks simulated
+final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3174528 # Simulator instruction rate (inst/s)
+host_op_rate 3174125 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1586983445 # Simulator tick rate (ticks/s)
+host_mem_usage 203780 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
+sim_insts 500001 # Number of instructions simulated
+sim_ops 500001 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 2872676 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 2000076 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 417562 # Number of bytes written to this memory
+system.physmem.num_reads 624454 # Number of read requests responded to by this memory
+system.physmem.num_writes 56340 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 11489991621 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999808012 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1670144451 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 13160136072 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 124435 # DTB read hits
+system.cpu.dtb.read_misses 8 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 124443 # DTB read accesses
+system.cpu.dtb.write_hits 56340 # DTB write hits
+system.cpu.dtb.write_misses 10 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 56350 # DTB write accesses
+system.cpu.dtb.data_hits 180775 # DTB hits
+system.cpu.dtb.data_misses 18 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 180793 # DTB accesses
+system.cpu.itb.fetch_hits 500019 # ITB hits
+system.cpu.itb.fetch_misses 13 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 500032 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 18 # Number of system calls
+system.cpu.numCycles 500032 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 500001 # Number of instructions committed
+system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
+system.cpu.num_func_calls 14357 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
+system.cpu.num_int_insts 474689 # number of integer instructions
+system.cpu.num_fp_insts 32 # number of float instructions
+system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
+system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
+system.cpu.num_mem_refs 180793 # number of memory refs
+system.cpu.num_load_insts 124443 # Number of load instructions
+system.cpu.num_store_insts 56350 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 500032 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------
-Traceback (most recent call last):
- File "<string>", line 1, in <module>
- File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main
- exec filecode in scope
- File "tests/run.py", line 78, in <module>
- execfile(joinpath(tests_root, category, mode, name, 'test.py'))
- File "tests/quick/se/20.eio-short/test.py", line 29, in <module>
- root.system.cpu.workload = EioProcess(file = binpath('anagram',
-NameError: name 'EioProcess' is not defined
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+hack: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:36:31
-gem5 started May 8 2012 15:37:07
-gem5 executing on piton
+gem5 compiled Feb 29 2012 00:47:21
+gem5 started Feb 29 2012 00:51:57
+gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 727929000 because a thread reached the max instruction count
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000728 # Number of seconds simulated
+sim_ticks 727929000 # Number of ticks simulated
+final_tick 727929000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1742138 # Simulator instruction rate (inst/s)
+host_op_rate 1742023 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2535976572 # Simulator tick rate (ticks/s)
+host_mem_usage 212652 # Number of bytes of host memory used
+host_seconds 0.29 # Real time elapsed on the host
+sim_insts 500001 # Number of instructions simulated
+sim_ops 500001 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 54848 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 857 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 75348008 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 35432027 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 75348008 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 124435 # DTB read hits
+system.cpu.dtb.read_misses 8 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 124443 # DTB read accesses
+system.cpu.dtb.write_hits 56340 # DTB write hits
+system.cpu.dtb.write_misses 10 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 56350 # DTB write accesses
+system.cpu.dtb.data_hits 180775 # DTB hits
+system.cpu.dtb.data_misses 18 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 180793 # DTB accesses
+system.cpu.itb.fetch_hits 500020 # ITB hits
+system.cpu.itb.fetch_misses 13 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 500033 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 18 # Number of system calls
+system.cpu.numCycles 1455858 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 500001 # Number of instructions committed
+system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
+system.cpu.num_func_calls 14357 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
+system.cpu.num_int_insts 474689 # number of integer instructions
+system.cpu.num_fp_insts 32 # number of float instructions
+system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
+system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
+system.cpu.num_mem_refs 180793 # number of memory refs
+system.cpu.num_load_insts 124443 # Number of load instructions
+system.cpu.num_store_insts 56350 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1455858 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.tagsinuse 264.952126 # Cycle average of tags in use
+system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu.icache.occ_percent::total 0.129371 # Average percentage of cache occupancy
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+system.cpu.icache.demand_hits::total 499617 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 499617 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 403 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses
+system.cpu.icache.overall_misses::total 403 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 22568000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 22568000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 22568000 # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total 22568000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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+system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 287.175167 # Cycle average of tags in use
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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+system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 16695000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7367000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7367000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24062000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 24062000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 481.419470 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::cpu.inst 264.958770 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 216.460700 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.008086 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.006606 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.014692 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 454 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 857 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses
+system.cpu.l2cache.overall_misses::total 857 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20956000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16380000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 37336000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7228000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 7228000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 20956000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 23608000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 44564000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 20956000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 23608000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 44564000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 403 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 315 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 139 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 139 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 403 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 454 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 857 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 403 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 454 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 718 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 857 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 857 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16120000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12600000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28720000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5560000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5560000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16120000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18160000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 34280000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16120000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18160000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 34280000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
-Traceback (most recent call last):
- File "<string>", line 1, in <module>
- File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main
- exec filecode in scope
- File "tests/run.py", line 78, in <module>
- execfile(joinpath(tests_root, category, mode, name, 'test.py'))
- File "tests/quick/se/30.eio-mp/test.py", line 29, in <module>
- process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz'))
-NameError: name 'EioProcess' is not defined
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+hack: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:36:31
-gem5 started May 8 2012 15:40:55
-gem5 executing on piton
+gem5 compiled Feb 29 2012 00:47:21
+gem5 started Feb 29 2012 00:51:57
+gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+>>>>Exiting @ tick 250015500 because a thread reached the max instruction count
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000250 # Number of seconds simulated
+sim_ticks 250015500 # Number of ticks simulated
+final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3384594 # Simulator instruction rate (inst/s)
+host_op_rate 3384489 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 423074550 # Simulator tick rate (ticks/s)
+host_mem_usage 1140672 # Number of bytes of host memory used
+host_seconds 0.59 # Real time elapsed on the host
+sim_insts 2000004 # Number of instructions simulated
+sim_ops 2000004 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 219392 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 103168 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 3428 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 877513594 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 412646416 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 877513594 # Total bandwidth to/from this memory (bytes/s)
+system.cpu0.dtb.fetch_hits 0 # ITB hits
+system.cpu0.dtb.fetch_misses 0 # ITB misses
+system.cpu0.dtb.fetch_acv 0 # ITB acv
+system.cpu0.dtb.fetch_accesses 0 # ITB accesses
+system.cpu0.dtb.read_hits 124435 # DTB read hits
+system.cpu0.dtb.read_misses 8 # DTB read misses
+system.cpu0.dtb.read_acv 0 # DTB read access violations
+system.cpu0.dtb.read_accesses 124443 # DTB read accesses
+system.cpu0.dtb.write_hits 56340 # DTB write hits
+system.cpu0.dtb.write_misses 10 # DTB write misses
+system.cpu0.dtb.write_acv 0 # DTB write access violations
+system.cpu0.dtb.write_accesses 56350 # DTB write accesses
+system.cpu0.dtb.data_hits 180775 # DTB hits
+system.cpu0.dtb.data_misses 18 # DTB misses
+system.cpu0.dtb.data_acv 0 # DTB access violations
+system.cpu0.dtb.data_accesses 180793 # DTB accesses
+system.cpu0.itb.fetch_hits 500019 # ITB hits
+system.cpu0.itb.fetch_misses 13 # ITB misses
+system.cpu0.itb.fetch_acv 0 # ITB acv
+system.cpu0.itb.fetch_accesses 500032 # ITB accesses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.read_acv 0 # DTB read access violations
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.write_acv 0 # DTB write access violations
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.data_hits 0 # DTB hits
+system.cpu0.itb.data_misses 0 # DTB misses
+system.cpu0.itb.data_acv 0 # DTB access violations
+system.cpu0.itb.data_accesses 0 # DTB accesses
+system.cpu0.workload.num_syscalls 18 # Number of system calls
+system.cpu0.numCycles 500032 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 500001 # Number of instructions committed
+system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses
+system.cpu0.num_func_calls 14357 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 474689 # number of integer instructions
+system.cpu0.num_fp_insts 32 # number of float instructions
+system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
+system.cpu0.num_mem_refs 180793 # number of memory refs
+system.cpu0.num_load_insts 124443 # Number of load instructions
+system.cpu0.num_store_insts 56350 # Number of store instructions
+system.cpu0.num_idle_cycles 0 # Number of idle cycles
+system.cpu0.num_busy_cycles 500032 # Number of busy cycles
+system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0 # Percentage of idle cycles
+system.cpu0.icache.replacements 152 # number of replacements
+system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use
+system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 499556 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 499556 # number of overall hits
+system.cpu0.icache.overall_hits::total 499556 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
+system.cpu0.icache.overall_misses::total 463 # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 500019 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 500019 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.replacements 61 # number of replacements
+system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits
+system.cpu0.dcache.overall_hits::total 180312 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
+system.cpu0.dcache.overall_misses::total 463 # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
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+system.cpu2.itb.fetch_accesses 500032 # ITB accesses
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+system.cpu2.itb.read_misses 0 # DTB read misses
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+system.cpu2.itb.data_accesses 0 # DTB accesses
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+system.cpu3.dtb.read_acv 0 # DTB read access violations
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+system.cpu3.dtb.write_acv 0 # DTB write access violations
+system.cpu3.dtb.write_accesses 56350 # DTB write accesses
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+system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
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+system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
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+system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
-Traceback (most recent call last):
- File "<string>", line 1, in <module>
- File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main
- exec filecode in scope
- File "tests/run.py", line 78, in <module>
- execfile(joinpath(tests_root, category, mode, name, 'test.py'))
- File "tests/quick/se/30.eio-mp/test.py", line 29, in <module>
- process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz'))
-NameError: name 'EioProcess' is not defined
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+hack: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:36:31
-gem5 started May 8 2012 15:36:56
-gem5 executing on piton
+gem5 compiled Feb 29 2012 00:47:21
+gem5 started Feb 29 2012 00:51:57
+gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+>>>>Exiting @ tick 728920000 because a thread reached the max instruction count
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000729 # Number of seconds simulated
+sim_ticks 728920000 # Number of ticks simulated
+final_tick 728920000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1560894 # Simulator instruction rate (inst/s)
+host_op_rate 1560871 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 568880584 # Simulator tick rate (ticks/s)
+host_mem_usage 223172 # Number of bytes of host memory used
+host_seconds 1.28 # Real time elapsed on the host
+sim_insts 1999954 # Number of instructions simulated
+sim_ops 1999954 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 219392 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 103168 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 3428 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 300982275 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 141535422 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 300982275 # Total bandwidth to/from this memory (bytes/s)
+system.cpu0.dtb.fetch_hits 0 # ITB hits
+system.cpu0.dtb.fetch_misses 0 # ITB misses
+system.cpu0.dtb.fetch_acv 0 # ITB acv
+system.cpu0.dtb.fetch_accesses 0 # ITB accesses
+system.cpu0.dtb.read_hits 124435 # DTB read hits
+system.cpu0.dtb.read_misses 8 # DTB read misses
+system.cpu0.dtb.read_acv 0 # DTB read access violations
+system.cpu0.dtb.read_accesses 124443 # DTB read accesses
+system.cpu0.dtb.write_hits 56340 # DTB write hits
+system.cpu0.dtb.write_misses 10 # DTB write misses
+system.cpu0.dtb.write_acv 0 # DTB write access violations
+system.cpu0.dtb.write_accesses 56350 # DTB write accesses
+system.cpu0.dtb.data_hits 180775 # DTB hits
+system.cpu0.dtb.data_misses 18 # DTB misses
+system.cpu0.dtb.data_acv 0 # DTB access violations
+system.cpu0.dtb.data_accesses 180793 # DTB accesses
+system.cpu0.itb.fetch_hits 500020 # ITB hits
+system.cpu0.itb.fetch_misses 13 # ITB misses
+system.cpu0.itb.fetch_acv 0 # ITB acv
+system.cpu0.itb.fetch_accesses 500033 # ITB accesses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.read_acv 0 # DTB read access violations
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.write_acv 0 # DTB write access violations
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.data_hits 0 # DTB hits
+system.cpu0.itb.data_misses 0 # DTB misses
+system.cpu0.itb.data_acv 0 # DTB access violations
+system.cpu0.itb.data_accesses 0 # DTB accesses
+system.cpu0.workload.num_syscalls 18 # Number of system calls
+system.cpu0.numCycles 1457840 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 500001 # Number of instructions committed
+system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed
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+system.cpu0.num_int_insts 474689 # number of integer instructions
+system.cpu0.num_fp_insts 32 # number of float instructions
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+system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
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+system.cpu0.num_busy_cycles 1457840 # Number of busy cycles
+system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0 # Percentage of idle cycles
+system.cpu0.icache.replacements 152 # number of replacements
+system.cpu0.icache.tagsinuse 216.390931 # Cycle average of tags in use
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+system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 216.390931 # Average occupied blocks per requestor
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+system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
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+system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
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+system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
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+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50699.784017 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50699.784017 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50699.784017 # average overall miss latency
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+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22085000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 22085000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22085000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 22085000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22085000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 22085000 # number of overall MSHR miss cycles
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+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47699.784017 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47699.784017 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47699.784017 # average overall mshr miss latency
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu0.dcache.overall_hits::total 180312 # number of overall hits
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+system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses
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+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52244.060475 # average overall mshr miss latency
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+system.cpu1.dtb.data_accesses 180792 # DTB accesses
+system.cpu1.itb.fetch_hits 500012 # ITB hits
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+system.cpu1.itb.fetch_accesses 500025 # ITB accesses
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+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.read_acv 0 # DTB read access violations
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+system.cpu1.itb.write_acv 0 # DTB write access violations
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+system.cpu1.itb.data_misses 0 # DTB misses
+system.cpu1.itb.data_acv 0 # DTB access violations
+system.cpu1.itb.data_accesses 0 # DTB accesses
+system.cpu1.workload.num_syscalls 18 # Number of system calls
+system.cpu1.numCycles 1457840 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
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+system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
+system.cpu1.num_func_calls 14357 # number of times a function call or return occured
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+system.cpu1.num_fp_insts 32 # number of float instructions
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+system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
+system.cpu1.num_mem_refs 180792 # number of memory refs
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+system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0 # Percentage of idle cycles
+system.cpu1.icache.replacements 152 # number of replacements
+system.cpu1.icache.tagsinuse 216.386658 # Cycle average of tags in use
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+system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 216.386658 # Average occupied blocks per requestor
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+system.cpu2.dcache.overall_hits::total 180309 # number of overall hits
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+system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses
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+system.cpu3.dtb.fetch_acv 0 # ITB acv
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+system.cpu3.dtb.read_accesses 124439 # DTB read accesses
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+system.cpu3.dtb.write_accesses 56349 # DTB write accesses
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+system.cpu3.dtb.data_misses 18 # DTB misses
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+system.cpu3.dtb.data_accesses 180788 # DTB accesses
+system.cpu3.itb.fetch_hits 499997 # ITB hits
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+system.cpu3.itb.data_accesses 0 # DTB accesses
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+system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
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+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47738.660907 # average overall mshr miss latency
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+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 55265.658747 # average overall miss latency
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+system.cpu3.dcache.writebacks::total 29 # number of writebacks
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+system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
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+system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7380000 # number of WriteReq MSHR miss cycles
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+system.cpu3.dcache.demand_mshr_miss_latency::total 24199000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24199000 # number of overall MSHR miss cycles
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40008.810573 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40007.444169 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40004.405286 # average overall mshr miss latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff