intel/isl: Allow valign2 for texture-only Y-tiled surfaces on gen7

The restriction that Y-tiled surfaces must have valign == 4 only aplies to
render targets but we were applying it universally.  This causes problems
if ISL_FORMAT_R32G32B32_FLOAT is used because it requires valign == 2; this
should be okay because you can't render to that format.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>

diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index 02273f83235f2f226c22345581063c82abd7d9c2..f3d8428d059f11b7d77c1f66d01fdba00f844a7e 100644 (file)
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -354,7 +354,8 @@ gen7_choose_valign_el(const struct isl_device *dev,
     */
    if (isl_surf_usage_is_depth(info->usage) ||
        info->samples > 1 ||
-       tiling == ISL_TILING_Y0) {
+       ((info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
+        tiling == ISL_TILING_Y0)) {
       require_valign4 = true;
    }