diffPil = true;
if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP))
diffCwp = true;
- if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
+ //if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
+ if(shared_data->cansave !=
+ thread->readIntReg(NumIntArchRegs + 3))
diffCansave = true;
+ //if(shared_data->canrestore !=
+ // thread->readMiscReg(MISCREG_CANRESTORE))
if(shared_data->canrestore !=
- thread->readMiscReg(MISCREG_CANRESTORE))
+ thread->readMiscReg(NumIntArchRegs + 4))
diffCanrestore = true;
- if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
+ //if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
+ if(shared_data->otherwin !=
+ thread->readIntReg(NumIntArchRegs + 5))
diffOtherwin = true;
- if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
+ //if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
+ if(shared_data->cleanwin !=
+ thread->readMiscReg(NumIntArchRegs + 6))
diffCleanwin = true;
+ for (int i = 0; i < 64; i++) {
+ if (shared_data->itb[i] != thread->getITBPtr()->TteRead(i))
+ diffTlb = true;
+ if (shared_data->dtb[i] != thread->getDTBPtr()->TteRead(i))
+ diffTlb = true;
+ }
+
if ((diffPC || diffCC || diffInst || diffRegs || diffTpc ||
diffTnpc || diffTstate || diffTt || diffHpstate ||
diffHtstate || diffHtba || diffPstate || diffY ||