(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 60e865b96b123e2666961f98d9c02ffee725cc0b..e2a314c32dc86db0f5eaf98c99ce9d1b3c302e74 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -315,3 +315,13 @@ left anaemic.  Fortunately, with the ISA Working Group being willing
 to consider RFCs (Requests For Change) these omissions have the potential
 to be corrected.
 
+One deliberate decision in SVP64 involves Predication. Typical Vector
+ISAs have quite comprehensive arithmetic and logical operations on
+Predicate Masks, and if CR Fields were the only predicates in SVP64
+it would put pressure on to start adding the exact same arithmetic and logical
+operations that already exist in the Integer opcodes.
+
+Instead of taking that route the decision was made to allow *both*
+Integer *and* CR Fields to be Predicate Masks, and to create Draft
+instructions that provide better transfer capability between CR Fields
+and Integer Register files.