+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
class L1Cache(BaseCache):
assoc = 2
block_size = 64
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
mshrs = 10
tgts_per_mshr = 20
is_top_level = True
class L2Cache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 20
tgts_per_mshr = 12
class PageTableWalkerCache(BaseCache):
assoc = 2
block_size = 64
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
defer_registration= False
# Instruction Cache
-# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
class O3_ARM_v7a_ICache(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 1
+ response_latency = 1
block_size = 64
mshrs = 2
tgts_per_mshr = 8
is_top_level = 'true'
# Data Cache
-# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
class O3_ARM_v7a_DCache(BaseCache):
- hit_latency = '2ns'
- response_latency = '2ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 6
tgts_per_mshr = 8
# TLB Cache
# Use a cache as a L2 TLB
class O3_ARM_v7aWalkCache(BaseCache):
- hit_latency = '4ns'
- response_latency = '4ns'
+ hit_latency = 4
+ response_latency = 4
block_size = 64
mshrs = 6
tgts_per_mshr = 8
# L2 Cache
-# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
class O3_ARM_v7aL2(BaseCache):
- hit_latency = '12ns'
- response_latency = '12ns'
+ hit_latency = 12
+ response_latency = 12
block_size = 64
mshrs = 16
tgts_per_mshr = 8
write_buffers = 8
prefetch_on_access = 'true'
# Simple stride prefetcher
- prefetcher = StridePrefetcher(degree=8, latency='1.0ns')
+ prefetcher = StridePrefetcher(degree=8, latency = 1)
else:
mem_size = SysConfig().mem()
if options.caches or options.l2cache:
- test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range])
+ test_sys.iocache = IOCache(clock = '1GHz',
+ addr_ranges=[test_sys.physmem.range])
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2005-2007 The Regents of The University of Michigan
# All rights reserved.
#
type = 'BaseCache'
assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes")
- hit_latency = Param.Latency("The hit latency for this cache")
- response_latency = Param.Latency(
+ hit_latency = Param.Cycles("The hit latency for this cache")
+ response_latency = Param.Cycles(
"Additional cache latency for the return path to core on a miss");
hash_delay = Param.Cycles(1, "time in cycles of hash access")
max_miss_count = Param.Counter(0,
addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
system(p->system)
{
+ // ensure the clock is not running at an unreasonable clock speed
+ if (clock == 1)
+ panic("Cache %s has a cycle time of 1 tick. Specify a clock.\n",
+ name());
}
void
/**
* The latency of a hit in this device.
*/
- const Tick hitLatency;
+ const Cycles hitLatency;
/**
* The latency of sending reponse to its upper level cache/core on a
* miss is much quicker that the hit latency. The responseLatency parameter
* tries to capture this latency.
*/
- const Tick responseLatency;
+ const Cycles responseLatency;
/** The number of targets for each MSHR. */
const int numTarget;
uint64_t order;
/** Stores time the cache blocked for statistics. */
- Tick blockedCycle;
+ Cycles blockedCycle;
/** Pointer to the MSHR that has no targets. */
MSHR *noTargetMSHR;
uint8_t flag = 1 << cause;
if (blocked == 0) {
blocked_causes[cause]++;
- blockedCycle = curTick();
+ blockedCycle = curCycle();
cpuSidePort->setBlocked();
}
blocked |= flag;
blocked &= ~flag;
DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
if (blocked == 0) {
- blocked_cycles[cause] += curTick() - blockedCycle;
+ blocked_cycles[cause] += curCycle() - blockedCycle;
cpuSidePort->clearBlocked();
}
}
* @return Boolean indicating whether the request was satisfied.
*/
bool access(PacketPtr pkt, BlkType *&blk,
- int &lat, PacketList &writebacks);
+ Cycles &lat, PacketList &writebacks);
/**
*Handle doing the Compare and Swap function for SPARC.
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
- * @return The result of the access.
+ * @return The number of ticks required for the access.
*/
Tick atomicAccess(PacketPtr pkt);
* Snoop for the provided request in the cache and return the estimated
* time of completion.
* @param pkt The memory request to snoop
- * @return The estimated completion time.
+ * @return The number of cycles required for the snoop.
*/
- Tick snoopAtomic(PacketPtr pkt);
+ Cycles snoopAtomic(PacketPtr pkt);
/**
* Squash all requests associated with specified thread.
template<class TagStore>
bool
Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
- int &lat, PacketList &writebacks)
+ Cycles &lat, PacketList &writebacks)
{
if (pkt->req->isUncacheable()) {
if (pkt->req->isClearLL()) {
pendingDelete.clear();
// we charge hitLatency for doing just about anything here
- Tick time = curTick() + hitLatency;
+ Tick time = clockEdge(hitLatency);
if (pkt->isResponse()) {
// must be cache-to-cache response from upper to lower level
return true;
}
- int lat = hitLatency;
+ Cycles lat = hitLatency;
BlkType *blk = NULL;
PacketList writebacks;
if (needsResponse) {
pkt->makeTimingResponse();
- cpuSidePort->schedTimingResp(pkt, curTick()+lat);
+ cpuSidePort->schedTimingResp(pkt, clockEdge(lat));
} else {
/// @todo nominally we should just delete the packet here,
/// however, until 4-phase stuff we can't because sending
Tick
Cache<TagStore>::atomicAccess(PacketPtr pkt)
{
- int lat = hitLatency;
+ Cycles lat = hitLatency;
// @TODO: make this a parameter
bool last_level_cache = false;
if (!last_level_cache) {
DPRINTF(Cache, "forwarding mem-inhibited %s on 0x%x\n",
pkt->cmdString(), pkt->getAddr());
- lat += memSidePort->sendAtomic(pkt);
+ lat += ticksToCycles(memSidePort->sendAtomic(pkt));
}
} else {
DPRINTF(Cache, "rcvd mem-inhibited %s on 0x%x: not responding\n",
CacheBlk::State old_state = blk ? blk->status : 0;
#endif
- lat += memSidePort->sendAtomic(bus_pkt);
+ lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt));
DPRINTF(Cache, "Receive response: %s for addr %x in state %i\n",
bus_pkt->cmdString(), bus_pkt->getAddr(), old_state);
void
Cache<TagStore>::handleResponse(PacketPtr pkt)
{
- Tick time = curTick() + hitLatency;
+ Tick time = clockEdge(hitLatency);
MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
bool is_error = pkt->isError();
// responseLatency is the latency of the return path
// from lower level caches/memory to an upper level cache or
// the core.
- completion_time = responseLatency +
+ completion_time = responseLatency * clock +
(transfer_offset ? pkt->finishTime : pkt->firstWordTime);
assert(!target->pkt->req->isUncacheable());
// responseLatency is the latency of the return path
// from lower level caches/memory to an upper level cache or
// the core.
- completion_time = responseLatency + pkt->finishTime;
+ completion_time = responseLatency * clock + pkt->finishTime;
target->pkt->req->setExtraData(0);
} else {
// not a cache fill, just forwarding response
// responseLatency is the latency of the return path
// from lower level cahces/memory to the core.
- completion_time = responseLatency + pkt->finishTime;
+ completion_time = responseLatency * clock + pkt->finishTime;
if (pkt->isRead() && !is_error) {
target->pkt->setData(pkt->getPtr<uint8_t>());
}
// invalidate it.
pkt->cmd = MemCmd::ReadRespWithInvalidate;
}
- memSidePort->schedTimingSnoopResp(pkt, curTick() + hitLatency);
+ memSidePort->schedTimingSnoopResp(pkt, clockEdge(hitLatency));
}
template<class TagStore>
}
template<class TagStore>
-Tick
+Cycles
Cache<TagStore>::snoopAtomic(PacketPtr pkt)
{
if (pkt->req->isUncacheable() || pkt->cmd == MemCmd::Writeback) {
-from m5.SimObject import SimObject
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+from ClockedObject import ClockedObject
from m5.params import *
from m5.proxy import *
-class BasePrefetcher(SimObject):
+class BasePrefetcher(ClockedObject):
type = 'BasePrefetcher'
abstract = True
size = Param.Int(100,
"Squash prefetches with a later time on a subsequent miss")
degree = Param.Int(1,
"Degree of the prefetch depth")
- latency = Param.Latency('10t',
- "Latency of the prefetcher")
+ latency = Param.Cycles('1', "Latency of the prefetcher")
use_master_id = Param.Bool(True,
"Use the master id to separate calculations of prefetches")
data_accesses_only = Param.Bool(False,
#include "sim/system.hh"
BasePrefetcher::BasePrefetcher(const Params *p)
- : SimObject(p), size(p->size), latency(p->latency), degree(p->degree),
+ : ClockedObject(p), size(p->size), latency(p->latency), degree(p->degree),
useMasterId(p->use_master_id), pageStop(!p->cross_pages),
serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
system(p->sys), masterId(system->getMasterId(name()))
std::list<Addr> addresses;
- std::list<Tick> delays;
+ std::list<Cycles> delays;
calculatePrefetch(pkt, addresses, delays);
std::list<Addr>::iterator addrIter = addresses.begin();
- std::list<Tick>::iterator delayIter = delays.begin();
+ std::list<Cycles>::iterator delayIter = delays.begin();
for (; addrIter != addresses.end(); ++addrIter, ++delayIter) {
Addr addr = *addrIter;
prefetch->req->setThreadContext(pkt->req->contextId(),
pkt->req->threadId());
- prefetch->time = time + (*delayIter); // @todo ADD LATENCY HERE
+ prefetch->time = time + clock * *delayIter;
// We just remove the head if we are full
if (pf.size() == size) {
#include "base/statistics.hh"
#include "mem/packet.hh"
#include "params/BaseCache.hh"
-#include "sim/sim_object.hh"
+#include "sim/clocked_object.hh"
class BaseCache;
-class BasePrefetcher : public SimObject
+class BasePrefetcher : public ClockedObject
{
protected:
int blkSize;
/** The latency before a prefetch is issued */
- Tick latency;
+ const Cycles latency;
/** The number of prefetches to issue */
unsigned degree;
virtual void calculatePrefetch(PacketPtr &pkt,
std::list<Addr> &addresses,
- std::list<Tick> &delays) = 0;
+ std::list<Cycles> &delays) = 0;
std::list<PacketPtr>::iterator inPrefetch(Addr address);
void
GHBPrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
- std::list<Tick> &delays)
+ std::list<Cycles> &delays)
{
Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
int master_id = useMasterId ? pkt->req->masterId() : 0;
~GHBPrefetcher() {}
void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
- std::list<Tick> &delays);
+ std::list<Cycles> &delays);
};
#endif // __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
void
StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
- std::list<Tick> &delays)
+ std::list<Cycles> &delays)
{
if (!pkt->req->hasPC()) {
DPRINTF(HWPrefetch, "ignoring request with no PC");
~StridePrefetcher() {}
void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
- std::list<Tick> &delays);
+ std::list<Cycles> &delays);
};
#endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
void
TaggedPrefetcher::
calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
- std::list<Tick> &delays)
+ std::list<Cycles> &delays)
{
Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1);
~TaggedPrefetcher() {}
void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
- std::list<Tick> &delays);
+ std::list<Cycles> &delays);
};
#endif // __MEM_CACHE_PREFETCH_TAGGED_PREFETCHER_HH__
using namespace std;
-FALRU::FALRU(unsigned _blkSize, unsigned _size, unsigned hit_latency)
+FALRU::FALRU(unsigned _blkSize, unsigned _size, Cycles hit_latency)
: blkSize(_blkSize), size(_size), hitLatency(hit_latency)
{
if (!isPowerOf2(blkSize))
}
FALRUBlk*
-FALRU::accessBlock(Addr addr, int &lat, int context_src, int *inCache)
+FALRU::accessBlock(Addr addr, Cycles &lat, int context_src, int *inCache)
{
accesses++;
int tmp_in_cache = 0;
/** The size of the cache. */
const unsigned size;
/** The hit latency of the cache. */
- const unsigned hitLatency;
+ const Cycles hitLatency;
/** Array of pointers to blocks at the cache size boundaries. */
FALRUBlk **cacheBoundaries;
* @param size The size of the cache.
* @param hit_latency The hit latency of the cache.
*/
- FALRU(unsigned blkSize, unsigned size, unsigned hit_latency);
+ FALRU(unsigned blkSize, unsigned size, Cycles hit_latency);
~FALRU();
/**
* @param inCache The FALRUBlk::inCache flags.
* @return Pointer to the cache block.
*/
- FALRUBlk* accessBlock(Addr addr, int &lat, int context_src, int *inCache = 0);
+ FALRUBlk* accessBlock(Addr addr, Cycles &lat, int context_src, int *inCache = 0);
/**
* Find the block in the cache, do not update the replacement data.
* Return the hit latency of this cache.
* @return The hit latency.
*/
- int getHitLatency() const
+ Cycles getHitLatency() const
{
return hitLatency;
}
IICTag*
-IIC::accessBlock(Addr addr, int &lat, int context_src)
+IIC::accessBlock(Addr addr, Cycles &lat, int context_src)
{
Addr tag = extractTag(addr);
unsigned set = hash(addr);
- int set_lat;
+ Cycles set_lat;
unsigned long chain_ptr = tagNull;
setAccess.sample(set);
IICTag *tag_ptr = sets[set].findTag(tag, chain_ptr);
- set_lat = 1;
+ set_lat = Cycles(1);
if (tag_ptr == NULL && chain_ptr != tagNull) {
int secondary_depth;
tag_ptr = secondaryChain(tag, chain_ptr, &secondary_depth);
- set_lat += secondary_depth;
+ set_lat += Cycles(secondary_depth);
// set depth for statistics fix this later!!! egh
sets[set].depth = set_lat;
}
}
- // @todo: is hashDelay is really cycles, then
- // multiply with period
- set_lat = set_lat * hashDelay + hitLatency;
+ set_lat = Cycles(set_lat * hashDelay + hitLatency);
if (tag_ptr != NULL) {
// IIC replacement: if this is not the first element of
// list, reorder
hitDepthTotal += sets[set].depth;
tag_ptr->status |= BlkReferenced;
lat = set_lat;
- if (tag_ptr->whenReady > curTick() && tag_ptr->whenReady - curTick() > set_lat) {
- lat = tag_ptr->whenReady - curTick();
+ if (tag_ptr->whenReady > curTick() &&
+ cache->ticksToCycles(tag_ptr->whenReady - curTick()) > set_lat) {
+ lat = cache->ticksToCycles(tag_ptr->whenReady - curTick());
}
tag_ptr->refCount += 1;
/** The associativity of the primary table. */
const unsigned assoc;
/** The base hit latency. */
- const unsigned hitLatency;
+ const Cycles hitLatency;
/** The subblock size, used for compression. */
const unsigned subSize;
/** The associativity of the primary table. */
unsigned assoc;
/** The number of cycles for each hash lookup. */
- unsigned hashDelay;
+ Cycles hashDelay;
/** The number of cycles to read the data. */
- unsigned hitLatency;
+ Cycles hitLatency;
/** The replacement policy. */
Repl *rp;
/** The subblock size in bytes. */
* @param lat The access latency.
* @return A pointer to the block found, if any.
*/
- IICTag* accessBlock(Addr addr, int &lat, int context_src);
+ IICTag* accessBlock(Addr addr, Cycles &lat, int context_src);
/**
* Find the block, do not update the replacement data.
}
LRU::BlkType*
-LRU::accessBlock(Addr addr, int &lat, int master_id)
+LRU::accessBlock(Addr addr, Cycles &lat, int master_id)
{
Addr tag = extractTag(addr);
unsigned set = extractSet(addr);
DPRINTF(CacheRepl, "set %x: moving blk %x to MRU\n",
set, regenerateBlkAddr(tag, set));
if (blk->whenReady > curTick()
- && blk->whenReady - curTick() > hitLatency) {
- lat = blk->whenReady - curTick();
+ && cache->ticksToCycles(blk->whenReady - curTick()) > hitLatency) {
+ lat = cache->ticksToCycles(blk->whenReady - curTick());
}
blk->refCount += 1;
}
/** The associativity of the cache. */
const unsigned assoc;
/** The hit latency. */
- const unsigned hitLatency;
+ const Cycles hitLatency;
/** The cache sets. */
CacheSet *sets;
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
- BlkType* accessBlock(Addr addr, int &lat, int context_src);
+ BlkType* accessBlock(Addr addr, Cycles &lat, int context_src);
/**
* Finds the given address in the cache, do not update replacement data.
* Return the hit latency.
* @return the hit latency.
*/
- int getHitLatency() const
+ Cycles getHitLatency() const
{
return hitLatency;
}
class MyCache(BaseCache):
assoc = 2
block_size = 64
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
mshrs = 10
tgts_per_mshr = 5
cpu = InOrderCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'),
- MyCache(size = '2MB', hit_latency='10ns',
- response_latency='10ns'))
+ MyCache(size = '2MB', hit_latency = 20,
+ response_latency = 20))
cpu.clock = '2GHz'
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 12
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
# l2cache & bus
system.toL2Bus = CoherentBus(clock="2GHz", width=16)
-system.l2c = L2(size='64kB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='64kB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
class MyCache(BaseCache):
assoc = 2
block_size = 64
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
mshrs = 10
tgts_per_mshr = 5
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'),
MyCache(size = '2MB'))
+# @todo Note that the L2 latency here is unmodified and 2 cycles,
+# should set hit latency and response latency to 20 cycles as for
+# other scripts
cpu.clock = '2GHz'
system = System(cpu = cpu,
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
# l2cache & bus
-system.toL2Bus = CoherentBus()
-system.l2c = L2(size='4MB', assoc=8)
+system.toL2Bus = CoherentBus(clock = '2GHz')
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
class MyCache(BaseCache):
assoc = 2
block_size = 64
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
mshrs = 10
tgts_per_mshr = 5
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'),
MyCache(size = '2MB'))
+# @todo Note that the L2 latency here is unmodified and 2 cycles,
+# should set hit latency and response latency to 20 cycles as for
+# other scripts
cpu.clock = '2GHz'
system = System(cpu = cpu,
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class PageTableWalkerCache(BaseCache):
assoc = 2
block_size = 64
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
system.cpu = cpu
#create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class PageTableWalkerCache(BaseCache):
assoc = 2
block_size = 64
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
system.cpu = cpu
#create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class PageTableWalkerCache(BaseCache):
assoc = 2
block_size = 64
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
system.cpu = cpu
#create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
cpu.addCheckerCpu()
#create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
system.cpu = cpus
#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
system.cpu = cpu
#create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
system.cpu = cpus
#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
system.cpu = cpu
#create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
system.cpu = cpus
#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
system.cpu = cpu
#create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
membus = CoherentBus())
# l2cache & bus
-system.toL2Bus = CoherentBus()
-system.l2c = L2(size='4MB', assoc=8)
+system.toL2Bus = CoherentBus(clock = '2GHz')
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
# l2cache & bus
-system.toL2Bus = CoherentBus()
-system.l2c = L2(size='4MB', assoc=8)
+system.toL2Bus = CoherentBus(clock = '2GHz')
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
class MyCache(BaseCache):
assoc = 2
block_size = 64
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
mshrs = 10
tgts_per_mshr = 5
cpu = TimingSimpleCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'),
- MyCache(size = '2MB', hit_latency='10ns', response_latency ='10ns'))
+ MyCache(size = '2MB', hit_latency= 20,
+ response_latency = 20))
system = System(cpu = cpu,
physmem = SimpleMemory(),
membus = CoherentBus())
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
system.cpu = cpu
#create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
system.cpu = cpus
#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
-system.iocache = IOCache()
+system.toL2Bus = CoherentBus(clock = '2GHz')
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
system.cpu = cpu
#create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
system.cpu = cpus
#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
system.cpu = cpu
#create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeLinuxAlphaSystem('timing')
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
system.cpu = cpus
#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
system.cpu = cpu
#create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
projects / gem5.git / commitdiff