translate clmul* to python for easier testing
authorJacob Lifshay <programmerjake@gmail.com>
Tue, 15 Mar 2022 08:41:15 +0000 (01:41 -0700)
committerJacob Lifshay <programmerjake@gmail.com>
Tue, 15 Mar 2022 08:41:15 +0000 (01:41 -0700)
openpower/__init__.py [new file with mode: 0644]
openpower/sv/__init__.py [new file with mode: 0644]
openpower/sv/bitmanip.mdwn
openpower/sv/bitmanip/__init__.py [new file with mode: 0644]
openpower/sv/bitmanip/clmul.py [new file with mode: 0644]
openpower/sv/bitmanip/clmulh.py [new file with mode: 0644]
openpower/sv/bitmanip/clmulr.py [new file with mode: 0644]

diff --git a/openpower/__init__.py b/openpower/__init__.py
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/openpower/sv/__init__.py b/openpower/sv/__init__.py
new file mode 100644 (file)
index 0000000..e69de29
index 6ce42a9917d1800868c58c4aa1b224c8e26e3e82..3774322ed9ef3756565e2ee06db30a683a39014e 100644 (file)
@@ -547,45 +547,18 @@ They are worth adding as their own non-overwrite operations
 
 ### `clmul` Carry-less Multiply
 
-```c
-uint_xlen_t clmul(uint_xlen_t RA, uint_xlen_t RB)
-{
-    uint_xlen_t x = 0;
-    for (int i = 0; i < XLEN; i++)
-        if ((RB >> i) & 1)
-            x ^= RA << i;
-    return x;
-}
-```
+[[!inline pagenames="openpower/sv/bitmanip/clmul.py" raw="true" feeds="no" actions="yes"]]
 
 ### `clmulh` Carry-less Multiply High
 
-```c
-uint_xlen_t clmulh(uint_xlen_t RA, uint_xlen_t RB)
-{
-    uint_xlen_t x = 0;
-    for (int i = 1; i < XLEN; i++)
-        if ((RB >> i) & 1)
-            x ^= RA >> (XLEN-i);
-    return x;
-}
-```
+[[!inline pagenames="openpower/sv/bitmanip/clmulh.py" raw="true" feeds="no" actions="yes"]]
 
 ### `clmulr` Carry-less Multiply (Reversed)
 
 Useful for CRCs. Equivalent to bit-reversing the result of `clmul` on
 bit-reversed inputs.
 
-```c
-uint_xlen_t clmulr(uint_xlen_t RA, uint_xlen_t RB)
-{
-    uint_xlen_t x = 0;
-    for (int i = 0; i < XLEN; i++)
-        if ((RB >> i) & 1)
-            x ^= RA >> (XLEN-i-1);
-    return x;
-}
-```
+[[!inline pagenames="openpower/sv/bitmanip/clmulr.py" raw="true" feeds="no" actions="yes"]]
 
 ## `clmadd` Carry-less Multiply-Add
 
diff --git a/openpower/sv/bitmanip/__init__.py b/openpower/sv/bitmanip/__init__.py
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/openpower/sv/bitmanip/clmul.py b/openpower/sv/bitmanip/clmul.py
new file mode 100644 (file)
index 0000000..7451c3c
--- /dev/null
@@ -0,0 +1,8 @@
+def clmul(a, b):
+    x = 0
+    i = 0
+    while b >> i != 0:
+        if (b >> i) & 1:
+            x ^= a << i
+        i += 1
+    return x
diff --git a/openpower/sv/bitmanip/clmulh.py b/openpower/sv/bitmanip/clmulh.py
new file mode 100644 (file)
index 0000000..b170aca
--- /dev/null
@@ -0,0 +1,5 @@
+from .clmul import clmul
+
+
+def clmulh(a, b, XLEN):
+    return clmul(a, b) >> XLEN
diff --git a/openpower/sv/bitmanip/clmulr.py b/openpower/sv/bitmanip/clmulr.py
new file mode 100644 (file)
index 0000000..5b155b5
--- /dev/null
@@ -0,0 +1,5 @@
+from .clmul import clmul
+
+
+def clmulh(a, b, XLEN):
+    return clmul(a, b) >> (XLEN - 1)