ARM: Fix SWP/SWPB undefined instruction behavior

SWP and SWPB now throw an undefined instruction exception if
SCTLR.SW == 0. This also required the MIDR to be changed
slightly so programs can correctly determine that gem5 supports
the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were
deprecated, but not disabled at CPU startup).

diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 16cb2e549fce94f2747c77416b5bd7529d51956b..9bd11041ae9e9dc44507906fdd30327a6c38fff7 100644 (file)
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -49,9 +49,9 @@ class ArmSystem(System):
     # 0x35 Implementor is '5' from "M5"
     # 0x0 Variant
     # 0xf Architecture from CPUID scheme
-    # 0xf00 Primary part number
+    # 0xc00 Primary part number ("c" or higher implies ARM v7)
     # 0x0 Revision
-    midr_regval = Param.UInt32(0x350ff000, "MIDR value")
+    midr_regval = Param.UInt32(0x350fc000, "MIDR value")
     boot_loader = Param.String("", "File that contains the boot loader code if any")
     boot_loader_mem = Param.PhysicalMemory(NULL,
                           "Memory object that boot loader is to be loaded into")

diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa
index 6a6ac837c600889f19f4a26bc57affd707d1fab5..3be4278fae03bc67e6aacbf6ed72a0e0e2547849 100644 (file)
--- a/src/arch/arm/isa/insts/swap.isa
+++ b/src/arch/arm/isa/insts/swap.isa
@@ -71,8 +71,18 @@ let {{
             decoder_output += newDecoder
             exec_output += newExec
 
+    swpPreAccCode = '''
+        if (!((SCTLR)Sctlr).sw) {
+#if FULL_SYSTEM
+            return new UndefinedInstruction;
+#else
+            return new UndefinedInstruction(false, mnemonic);
+#endif
+        }
+    '''
+
     SwapInst('swp', 'Swp', 'EA = Base;',
-             'Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);',
+             swpPreAccCode + 'Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);',
              'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);',
              ['Request::MEM_SWAP',
               'ArmISA::TLB::AlignWord',
@@ -80,7 +90,7 @@ let {{
               ['IsStoreConditional']).emit()
 
     SwapInst('swpb', 'Swpb', 'EA = Base;',
-             'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);',
+             swpPreAccCode + 'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);',
              'Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);',
              ['Request::MEM_SWAP',
               'ArmISA::TLB::AlignByte',