* gencode.c (write_opcodes): Output hex values for opcode mask

	and patterns.
	* interp.c (sim_resume):  Save and restore PC from the appropriate
	register.
	* (sim_fetch_register sim_store_register):  Fix byte-order problem
	with reading and writing registers.
	* simops.c (OP_FFFF):  Implement pseudo-breakpoint insn.

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index e26b49c0de153d4f9b1dd611178cc7411a565f63..5d4920faeccc7f8235e208e84dca0c8e90537860 100644 (file)
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,13 @@
+Fri Sep 27 18:34:09 1996  Stu Grossman  (grossman@critters.cygnus.com)
+
+       * gencode.c (write_opcodes):  Output hex values for opcode mask
+       and patterns.
+       * interp.c (sim_resume):  Save and restore PC from the appropriate
+       register.
+       * (sim_fetch_register sim_store_register):  Fix byte-order problem
+       with reading and writing registers.
+       * simops.c (OP_FFFF):  Implement pseudo-breakpoint insn.
+
 Fri Sep 27 17:42:37 1996  Jeffrey A Law  (law@cygnus.com)
 
        * simops.c (trace_input): Fix thinko. 

diff --git a/sim/v850/gencode.c b/sim/v850/gencode.c
index 3e98ace45a986f3507f6725c28a600b3bed9cab4..a637fe2578e695ab7c0ec0a632a42490c0bc7ffb 100644 (file)
--- a/sim/v850/gencode.c
+++ b/sim/v850/gencode.c
@@ -94,7 +94,7 @@ write_opcodes ()
   
   for (opcode = (struct v850_opcode *)v850_opcodes; opcode->name; opcode++)
     {
-      printf ("  { %ld,%ld,OP_%X,",
+      printf ("  { 0x%x,0x%x,OP_%X,",
              opcode->opcode, opcode->mask, opcode->opcode);
       
       Opcodes[curop++] = opcode->opcode;

diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index ce707432e881889de3d40e9228c3f15072ffab18..77b7c6658c1a2451656692478a0549824d3e933c 100644 (file)
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -287,10 +287,10 @@ sim_open (args)
     {
 #ifdef DEBUG
       if (strcmp (args, "-t") == 0)
-       d10v_debug = DEBUG;
+       v850_debug = DEBUG;
       else
 #endif
-       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",args);
+       (*v850_callback->printf_filtered) (v850_callback, "ERROR: unsupported option(s): %s\n",args);
     }
 
   /* put all the opcodes in the hash table */
@@ -342,6 +342,8 @@ sim_resume (step, siggnal)
   uint32 inst, opcode;
   reg_t oldpc;
 
+  PC = State.sregs[0];
+
  if (step)
    State.exception = SIGTRAP;
  else
@@ -399,6 +401,8 @@ sim_resume (step, siggnal)
        }
    } 
  while (!State.exception);
+
+  State.sregs[0] = PC;
 }
 
 int
@@ -462,7 +466,7 @@ sim_fetch_register (rn, memory)
      int rn;
      unsigned char *memory;
 {
-  *(uint32 *)memory = State.regs[rn];
+  put_word (memory, State.regs[rn]);
 }
  
 void
@@ -470,7 +474,7 @@ sim_store_register (rn, memory)
      int rn;
      unsigned char *memory;
 {
-  State.regs[rn]= *(uint32 *)memory;
+  State.regs[rn] = get_word (memory);
 }
 
 int

diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 07d9ae20797e9f09b9e7c975a8a8b688c4b7aab1..0b92c89ec19899c560623f9b3b2981572758d34c 100644 (file)
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -1898,6 +1898,14 @@ OP_C7C0 ()
   trace_output (OP_BIT);
 }
 
+/* breakpoint */
+void
+OP_FFFF ()
+{
+  State.exception = SIGTRAP;
+  PC -= 4;
+}
+
 /* di */
 void
 OP_16007E0 ()