addDff -> addDffGate as per @daveshah1

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 154581179f830a2b73b9ce4011125de9dafd14ea..c45de8531796ef2aa5b9063756d219abd808a0b3 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -176,7 +176,7 @@ void AigerReader::parse_aiger_ascii()
         RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
         RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
 
-        module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
+        module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
 
         // Reset logic is optional in AIGER 1.9
         if (f.peek() == ' ') {