update LiteScope

diff --git a/README b/README
index 901bb281223b6aa993a06406306ddba1efe80c0f..1080794c542ac19a81ca05f12419cbd30119d91c 100644 (file)
--- a/README
+++ b/README
@@ -12,7 +12,7 @@
 ---------
 LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
 
-LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex
+LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex
 FPGA IP cores by providing simple, elegant and efficient implementations of
 components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
 

diff --git a/targets/bist.py b/targets/bist.py
index 9d8031490dafaa4b4404ab9f82ced5e8b99a1d69..118d3a1ac139cc349d863ddbcf8ba132ce60fd9d 100644 (file)
--- a/targets/bist.py
+++ b/targets/bist.py
@@ -13,7 +13,7 @@ from misoclib import identifier
 from litescope.common import *
 from litescope.bridge.uart2wb import LiteScopeUART2WB
 from litescope.frontend.la import LiteScopeLA
-from litescope.core.trigger import LiteScopeTerm
+from litescope.core.port import LiteScopeTerm
 
 from litesata.common import *
 from litesata.phy import LiteSATAPHY
@@ -164,7 +164,7 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
                self.sata_core_command_rx_fsm_state = Signal(4)
                self.sata_core_command_tx_fsm_state = Signal(4)
 
-               self.debug = (
+               debug = (
                        self.sata_phy.ctrl.ready,
 
                        self.sata_phy.source.stb,
@@ -201,8 +201,8 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
                        self.sata_core_command_tx_fsm_state,
                )
 
-               self.submodules.la = LiteScopeLA(2048, self.debug)
-               self.la.add_port(LiteScopeTerm)
+               self.submodules.la = LiteScopeLA(debug, 2048)
+               self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
                atexit.register(self.exit, platform)
 
        def do_finalize(self):
@@ -218,6 +218,6 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
 
        def exit(self, platform):
                if platform.vns is not None:
-                       self.la.export(self.debug, platform.vns, "./test/la.csv")
+                       self.la.export(platform.vns, "../test/la.csv")
 
 default_subtarget = BISTSoC

diff --git a/test/test_la.py b/test/test_la.py
index 436bc9e2af6321a2d9d131da7f8e213b95c07779..66867c9b8e73dd61b9d185dcc73254c1318373b2 100644 (file)
--- a/test/test_la.py
+++ b/test/test_la.py
@@ -44,19 +44,21 @@ conditions["rd_resp"] = {
        "sata_command_rx_source_payload_read"   : 1,
 }
 
-la.prog_term(port=0, cond=conditions[trig])
-la.prog_sum("term")
+la.configure_term(port=0, cond=conditions[trig])
+la.configure_sum("term")
 
-# Trigger / wait / receive
-la.trigger(offset=64, length=1024)
+# Run Logic Analyzer
+la.run(offset=64, length=1024)
 
 #identify.run(blocking=False)
 generator.run(0, 2, 1, 0, blocking=False)
 #checker.run(0, 2, 1, 0, blocking=False)
-la.wait_done()
 
-la.read()
-la.export("dump.vcd")
+while not la.done():
+       pass
+
+la.upload()
+la.save("dump.vcd")
 ###
 wb.close()