projects
/
nmigen.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
3bc3647
)
pysim.back: fix add_sync_process wrapper to handle signals correctly.
author
whitequark
<whitequark@whitequark.org>
Fri, 14 Dec 2018 16:21:53 +0000
(16:21 +0000)
committer
whitequark
<whitequark@whitequark.org>
Fri, 14 Dec 2018 16:21:53 +0000
(16:21 +0000)
nmigen/back/pysim.py
patch
|
blob
|
history
diff --git
a/nmigen/back/pysim.py
b/nmigen/back/pysim.py
index ba32dbf2c858f80dbf7be6f728065d49749e9dc9..f0bfba101370af2b1723eaa8c778e9daf58a729f 100644
(file)
--- a/
nmigen/back/pysim.py
+++ b/
nmigen/back/pysim.py
@@
-243,7
+243,9
@@
class Simulator:
try:
result = process.send(None)
while True:
- result = process.send((yield (result or Tick(domain))))
+ if result is None:
+ result = Tick(domain)
+ result = process.send((yield result))
except StopIteration:
pass
self.add_process(sync_process())